Lines Matching refs:xf
867 rm = (insn) & 0xf;
888 val = (insn & 0xf) | ((insn >> 4) & 0xf0);
898 rm = (insn) & 0xf;
1326 rd = (insn >> 16) & 0xf;
1356 int rd = (insn >> 0) & 0xf;
1387 wrd = insn & 0xf;
1388 rdlo = (insn >> 12) & 0xf;
1389 rdhi = (insn >> 16) & 0xf;
1403 wrd = (insn >> 12) & 0xf;
1410 if ((insn >> 28) == 0xf) { /* WLDRW wCx */
1437 if ((insn >> 28) == 0xf) { /* WSTRW wCx */
1471 wrd = (insn >> 12) & 0xf;
1472 rd0 = (insn >> 0) & 0xf;
1473 rd1 = (insn >> 16) & 0xf;
1482 if (insn & 0xf)
1484 rd = (insn >> 12) & 0xf;
1485 wrd = (insn >> 16) & 0xf;
1513 wrd = (insn >> 12) & 0xf;
1514 rd0 = (insn >> 0) & 0xf;
1515 rd1 = (insn >> 16) & 0xf;
1524 if (insn & 0xf)
1526 rd = (insn >> 12) & 0xf;
1527 wrd = (insn >> 16) & 0xf;
1532 wrd = (insn >> 12) & 0xf;
1533 rd0 = (insn >> 0) & 0xf;
1534 rd1 = (insn >> 16) & 0xf;
1544 wrd = (insn >> 12) & 0xf;
1545 rd0 = (insn >> 0) & 0xf;
1546 rd1 = (insn >> 16) & 0xf;
1555 wrd = (insn >> 12) & 0xf;
1556 rd0 = (insn >> 0) & 0xf;
1557 rd1 = (insn >> 16) & 0xf;
1567 wrd = (insn >> 12) & 0xf;
1568 rd0 = (insn >> 16) & 0xf;
1569 rd1 = (insn >> 0) & 0xf;
1589 wrd = (insn >> 12) & 0xf;
1590 rd0 = (insn >> 16) & 0xf;
1591 rd1 = (insn >> 0) & 0xf;
1611 wrd = (insn >> 12) & 0xf;
1612 rd0 = (insn >> 16) & 0xf;
1613 rd1 = (insn >> 0) & 0xf;
1625 wrd = (insn >> 12) & 0xf;
1626 rd0 = (insn >> 16) & 0xf;
1627 rd1 = (insn >> 0) & 0xf;
1644 wrd = (insn >> 12) & 0xf;
1645 rd0 = (insn >> 16) & 0xf;
1646 rd1 = (insn >> 0) & 0xf;
1660 wrd = (insn >> 12) & 0xf;
1661 rd0 = (insn >> 16) & 0xf;
1662 rd1 = (insn >> 0) & 0xf;
1682 wrd = (insn >> 12) & 0xf;
1683 rd0 = (insn >> 16) & 0xf;
1684 rd1 = (insn >> 0) & 0xf;
1702 wrd = (insn >> 12) & 0xf;
1703 rd0 = (insn >> 16) & 0xf;
1704 rd1 = (insn >> 0) & 0xf;
1717 rd = (insn >> 12) & 0xf;
1718 wrd = (insn >> 16) & 0xf;
1746 rd = (insn >> 12) & 0xf;
1747 wrd = (insn >> 16) & 0xf;
1800 rd = (insn >> 12) & 0xf;
1801 wrd = (insn >> 16) & 0xf;
1847 wrd = (insn >> 12) & 0xf;
1848 rd0 = (insn >> 16) & 0xf;
1895 rd = (insn >> 12) & 0xf;
1896 rd0 = (insn >> 16) & 0xf;
1897 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3)
1916 wrd = (insn >> 12) & 0xf;
1917 rd0 = (insn >> 16) & 0xf;
1918 rd1 = (insn >> 0) & 0xf;
1948 wrd = (insn >> 12) & 0xf;
1949 rd0 = (insn >> 16) & 0xf;
1979 wrd = (insn >> 12) & 0xf;
1980 rd0 = (insn >> 16) & 0xf;
2012 wrd = (insn >> 12) & 0xf;
2013 rd0 = (insn >> 16) & 0xf;
2040 wrd = (insn >> 12) & 0xf;
2041 rd0 = (insn >> 16) & 0xf;
2068 wrd = (insn >> 12) & 0xf;
2069 rd0 = (insn >> 16) & 0xf;
2096 wrd = (insn >> 12) & 0xf;
2097 rd0 = (insn >> 16) & 0xf;
2102 if (gen_iwmmxt_shift(insn, 0xf, tmp)) {
2130 wrd = (insn >> 12) & 0xf;
2131 rd0 = (insn >> 16) & 0xf;
2132 rd1 = (insn >> 0) & 0xf;
2161 wrd = (insn >> 12) & 0xf;
2162 rd0 = (insn >> 16) & 0xf;
2163 rd1 = (insn >> 0) & 0xf;
2192 wrd = (insn >> 12) & 0xf;
2193 rd0 = (insn >> 16) & 0xf;
2194 rd1 = (insn >> 0) & 0xf;
2207 wrd = (insn >> 12) & 0xf;
2208 rd0 = (insn >> 16) & 0xf;
2209 rd1 = (insn >> 0) & 0xf;
2211 switch ((insn >> 20) & 0xf) {
2250 wrd = (insn >> 12) & 0xf;
2251 rd0 = (insn >> 16) & 0xf;
2264 wrd = (insn >> 12) & 0xf;
2265 rd0 = (insn >> 16) & 0xf;
2266 rd1 = (insn >> 0) & 0xf;
2268 switch ((insn >> 20) & 0xf) {
2309 wrd = (insn >> 12) & 0xf;
2310 rd0 = (insn >> 16) & 0xf;
2311 rd1 = (insn >> 0) & 0xf;
2341 wrd = (insn >> 5) & 0xf;
2342 rd0 = (insn >> 12) & 0xf;
2343 rd1 = (insn >> 0) & 0xf;
2344 if (rd0 == 0xf || rd1 == 0xf)
2349 switch ((insn >> 16) & 0xf) {
2356 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */
2389 rd0 = (insn >> 12) & 0xf;
2390 rd1 = insn & 0xf;
2398 switch ((insn >> 16) & 0xf) {
2408 case 0xf: /* MIATT */
2427 rdhi = (insn >> 16) & 0xf;
2428 rdlo = (insn >> 12) & 0xf;
2455 uint32_t rd = (insn >> 12) & 0xf;
2456 uint32_t cp = (insn >> 8) & 0xf;
2482 int cpn = (insn >> 16) & 0xf;
2483 int cpm = insn & 0xf;
2503 int cpn = (insn >> 16) & 0xf;
2504 int cpm = insn & 0xf;
2607 rd = (insn >> 12) & 0xf;
2740 rn = (insn >> 16) & 0xf;
2746 switch ((insn >> 24) & 0xf) {
2750 rd = (insn >> 12) & 0xf;
2756 if (insn & 0xf)
3113 i = ((insn >> 12) & 0x70) | (insn & 0xf);
3325 rn = (insn >> 16) & 0xf;
3326 rd = (insn >> 12) & 0xf;
3370 rn = (insn >> 16) & 0xf;
3847 rn = (insn >> 16) & 0xf;
3848 rm = insn & 0xf;
3852 op = (insn >> 8) & 0xf;
3933 int idx = (insn >> 4) & 0xf;
4273 [NEON_3R_VQADD] = 0xf,
4275 [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
4277 [NEON_3R_VQSUB] = 0xf,
4280 [NEON_3R_VSHL] = 0xf,
4281 [NEON_3R_VQSHL] = 0xf,
4282 [NEON_3R_VRSHL] = 0xf,
4283 [NEON_3R_VQRSHL] = 0xf,
4288 [NEON_3R_VADD_VSUB] = 0xf,
4841 op = (insn >> 8) & 0xf;
5186 op = (insn >> 8) & 0xf;
5188 imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
5266 op = (insn >> 8) & 0xf;
5607 imm = (insn >> 8) & 0xf;
5662 op = ((insn >> 12) & 0x30) | ((insn >> 7) & 0xf);
6080 int crn = (insn >> 16) & 0xf;
6081 int crm = insn & 0xf;
6084 int rt = (insn >> 12) & 0xf;
6140 int crn = (insn >> 16) & 0xf;
6141 int crm = insn & 0xf;
6144 int rt = (insn >> 12) & 0xf;
6199 cpnum = (insn >> 8) & 0xf;
6437 if (cond == 0xf){
6498 switch ((insn >> 4) & 0xf) {
6563 rn = (insn >> 16) & 0xf;
6668 rd = (insn >> 12) & 0xf;
6682 if (((insn >> 12) & 0xf) != 0xf)
6684 if (((insn >> 16) & 0xf) == 0) {
6689 shift = ((insn >> 8) & 0xf) * 2;
6693 if (gen_set_psr_im(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, val))
6701 sh = (insn >> 4) & 0xf;
6702 rm = insn & 0xf;
6709 if (gen_set_psr(s, msr_mask(env, s, (insn >> 16) & 0xf, i), i, tmp))
6713 rd = (insn >> 12) & 0xf;
6734 rd = (insn >> 12) & 0xf;
6766 rd = (insn >> 12) & 0xf;
6767 rn = (insn >> 16) & 0xf;
6799 rs = (insn >> 8) & 0xf;
6800 rn = (insn >> 12) & 0xf;
6801 rd = (insn >> 16) & 0xf;
6852 op1 = (insn >> 21) & 0xf;
6860 shift = ((insn >> 8) & 0xf) * 2;
6871 rm = (insn) & 0xf;
6878 rs = (insn >> 8) & 0xf;
6884 rn = (insn >> 16) & 0xf;
6889 rd = (insn >> 12) & 0xf;
7030 op1 = (insn >> 24) & 0xf;
7038 rd = (insn >> 16) & 0xf;
7039 rn = (insn >> 12) & 0xf;
7040 rs = (insn >> 8) & 0xf;
7041 rm = (insn) & 0xf;
7042 op1 = (insn >> 20) & 0xf;
7100 rn = (insn >> 16) & 0xf;
7101 rd = (insn >> 12) & 0xf;
7129 rm = insn & 0xf;
7150 rm = (insn) & 0xf;
7172 rn = (insn >> 16) & 0xf;
7173 rd = (insn >> 12) & 0xf;
7248 rm = insn & 0xf;
7249 rn = (insn >> 16) & 0xf;
7250 rd = (insn >> 12) & 0xf;
7251 rs = (insn >> 8) & 0xf;
7498 sh = (0xf << 20) | (0xf << 4);
7504 rn = (insn >> 16) & 0xf;
7505 rd = (insn >> 12) & 0xf;
7553 rn = (insn >> 16) & 0xf;
7683 case 0xf:
7844 rn = (insn >> 16) & 0xf;
7845 rs = (insn >> 12) & 0xf;
7846 rd = (insn >> 8) & 0xf;
7847 rm = insn & 0xf;
7848 switch ((insn >> 25) & 0xf) {
8058 op = (insn >> 21) & 0xf;
8208 op = (insn >> 4) & 0xf;
8304 op = ((insn >> 4) & 0xf) | ((insn >> 16) & 0x70);
8440 msr_mask(env, s, (insn >> 8) & 0xf, op == 1),
8473 op = (insn >> 4) & 0xf;
8525 op = (insn >> 22) & 0xf;
8678 rn = (insn >> 16) & 0xf;
8685 op = (insn >> 21) & 0xf;
8690 rd = (insn >> 8) & 0xf;
8764 switch ((insn >> 8) & 0xf) {
8766 shift = (insn >> 4) & 0xf;
8794 case 0xf: /* Pre-increment. */
8973 rm = (insn >> 3) & 0xf;
9013 op = (insn >> 6) & 0xf;
9027 } else if (op != 0xf) { /* mvn doesn't read its first operand */
9124 case 0xf: /* mvn */
9135 if (op != 0xf)
9289 op = (insn >> 8) & 0xf;
9387 if ((insn & 0xf) == 0) {
9388 gen_nop_hint(s, (insn >> 4) & 0xf);
9490 cond = (insn >> 8) & 0xf;
9494 if (cond == 0xf) {
9567 dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
9877 cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26);
