Lines Matching refs:ULL
302 #define AMD64G_CC_MASK_O (1ULL << AMD64G_CC_SHIFT_O)
303 #define AMD64G_CC_MASK_S (1ULL << AMD64G_CC_SHIFT_S)
304 #define AMD64G_CC_MASK_Z (1ULL << AMD64G_CC_SHIFT_Z)
305 #define AMD64G_CC_MASK_A (1ULL << AMD64G_CC_SHIFT_A)
306 #define AMD64G_CC_MASK_C (1ULL << AMD64G_CC_SHIFT_C)
307 #define AMD64G_CC_MASK_P (1ULL << AMD64G_CC_SHIFT_P)
315 #define AMD64G_FC_MASK_C3 (1ULL << AMD64G_FC_SHIFT_C3)
316 #define AMD64G_FC_MASK_C2 (1ULL << AMD64G_FC_SHIFT_C2)
317 #define AMD64G_FC_MASK_C1 (1ULL << AMD64G_FC_SHIFT_C1)
318 #define AMD64G_FC_MASK_C0 (1ULL << AMD64G_FC_SHIFT_C0)
