Lines Matching defs:fD
11781 // FTO{S,U}ID fD, dM
11787 UInt fD = (INSN(15,12) << 1) | bD;
11796 putFReg(fD, unop(Iop_ReinterpI32asF32,
11801 nCC(conq), fD, dM);
11804 putFReg(fD, unop(Iop_ReinterpI32asF32,
11809 nCC(conq), fD, dM);
11822 C4-98, C5-26 1 FSTMD cond 1100 1x00 Rn Fd 1010 offset
11823 C4-98, C5-28 2 FSTMDIA cond 1100 1x10 Rn Fd 1010 offset
11824 C4-98, C5-30 3 FSTMDDB cond 1101 0x10 Rn Fd 1010 offset
11826 C4-40, C5-26 1 FLDMD cond 1100 1x01 Rn Fd 1010 offset
11827 C4-40, C5-26 2 FLDMIAD cond 1100 1x11 Rn Fd 1010 offset
11828 C4-40, C5-26 3 FLDMDBD cond 1101 0x11 Rn Fd 1010 offset
11830 Regs transferred: F(Fd:D) .. F(Fd:d + offset)
11848 UInt fD = (INSN(15,12) << 1) | bD;
11873 if (fD + nRegs - 1 >= 32)
11920 putFReg(fD + i, loadLE(Ity_F32, addr), IRTemp_INVALID);
11922 storeLE(addr, getFReg(fD + i));
11939 nm, nCC(conq), rN, fD, fD + nRegs - 1);
11942 nm, nCC(conq), rN, fD, fD + nRegs - 1);
11945 nm, nCC(conq), rN, fD, fD + nRegs - 1);
11995 UInt fD = (INSN(15,12) << 1) | bD;
12014 putFReg(fD, loadLE(Ity_F32,mkexpr(ea)), IRTemp_INVALID);
12016 storeLE(mkexpr(ea), getFReg(fD));
12019 bL ? "ld" : "st", nCC(conq), fD, rN,
12032 UInt fD = (INSN(15,12) << 1) | bD; /* dst/acc */
12042 putFReg(fD
12043 getFReg(fD),
12046 DIP("fmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
12049 putFReg(fD, triop(Iop_AddF32, rm,
12050 getFReg(fD),
12055 DIP("fnmacs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
12058 putFReg(fD, triop(Iop_AddF32, rm,
12059 unop(Iop_NegF32, getFReg(fD)),
12062 DIP("fmscs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
12065 putFReg(fD, triop(Iop_AddF32, rm,
12066 unop(Iop_NegF32, getFReg(fD)),
12072 DIP("fnmscs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
12075 putFReg(fD, triop(Iop_MulF32, rm, getFReg(fN), getFReg(fM)),
12077 DIP("fmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
12080 putFReg(fD, unop(Iop_NegF32,
12084 DIP("fnmuls%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
12087 putFReg(fD, triop(Iop_AddF32, rm, getFReg(fN), getFReg(fM)),
12089 DIP("fadds%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
12092 putFReg(fD, triop(Iop_SubF32, rm, getFReg(fN), getFReg(fM)),
12094 DIP("fsubs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
12097 putFReg(fD, triop(Iop_DivF32, rm, getFReg(fN), getFReg(fM)),
12099 DIP("fdivs%s s%u, s%u, s%u\n", nCC(conq), fD, fN, fM);
12109 FCMPS cond 1110 1D11 0100 Fd 1010 01M0 Fm
12110 FCMPES cond 1110 1D11 0100 Fd 1010 11M0 Fm
12111 FCMPZS cond 1110 1D11 0101 Fd 1010 0100 0000
12112 FCMPZED cond 1110 1D11 0101 Fd 1010 1100 0000
12115 Z=0 Compare Fd:D vs Fm:M and set FPSCR 31:28 accordingly
12116 Z=1 Compare Fd:D vs zero
12130 UInt fD = (INSN(15,12) << 1) | bD;
12139 assign(argL, unop(Iop_F32toF64, getFReg(fD)));
12173 DIP("fcmpz%ss%s s%u\n", bN ? "e" : "", nCC(conq), fD);
12176 nCC(conq), fD, fM);
12190 UInt fD = (INSN(15,12) << 1) | bD;
12196 putFReg(fD, getFReg(fM), condT);
12197 DIP("fcpys%s s%u, s%u\n", nCC(conq), fD, fM);
12202 putFReg(fD, unop(Iop_AbsF32, getFReg(fM)), condT);
12203 DIP("fabss%s s%u, s%u\n", nCC(conq), fD, fM);
12208 putFReg(fD, unop(Iop_NegF32, getFReg(fM)), condT);
12209 DIP("fnegs%s s%u, s%u\n", nCC(conq), fD, fM);
12215 putFReg(fD, binop(Iop_SqrtF32, rm, getFReg(fM)), condT);
12216 DIP("fsqrts%s s%u, s%u\n", nCC(conq), fD, fM);
12227 // F{S,U}ITOS fD, fM
12240 UInt fD = (INSN(15,12) << 1) | bD;
12246 putFReg(fD, binop(Iop_F64toF32,
12251 DIP("fsitos%s s%u, s%u\n", nCC(conq), fD, fM);
12254 putFReg(fD, binop(Iop_F64toF32,
12259 DIP("fuitos%s s%u, s%u\n", nCC(conq), fD, fM);
12264 // FTO{S,U}IS fD, fM
12271 UInt fD = (INSN(15,12) << 1) | bD;
12280 putFReg(fD, unop(Iop_ReinterpI32asF32,
12285 nCC(conq), fD, fM);
12289 putFReg(fD, unop(Iop_ReinterpI32asF32,
12294 nCC(conq), fD, fM);
12320 UInt fD = (INSN(15,12) << 1) | bD;
12324 putFReg(fD, binop(Iop_F64toF32, mkexpr(rmode), getDReg(dM)),
12326 DIP("fcvtsd%s s%u, d%u\n", nCC(conq), fD, dM);
