Lines Matching refs:rex
2023 (lowest bit of rex distinguishes R12/RSP)
2027 (lowest bit of rex distinguishes R12/RSP)
2122 /* Clear the W bit on a REX byte, thereby changing the operand size
2124 static inline UChar clearWBit ( UChar rex )
2126 return toUChar(rex & ~(1<<3));
2130 /* Make up a REX byte, with W=1 (size=64), for a (greg,amode) pair. */
2151 /* Make up a REX byte, with W=1 (size=64), for a (greg,ereg) pair. */
2269 UChar rex;
2543 rex = clearWBit( rexAMode_R( fake(0), i->Ain.Alu32R.dst ) );
2544 if (rex != 0x40) *p++ = rex;
2549 rex = clearWBit( rexAMode_R( fake(0), i->Ain.Alu32R.dst) );
2550 if (rex != 0x40) *p++ = rex;
2557 rex = clearWBit(
2560 if (rex != 0x40) *p++ = rex;
2566 rex = clearWBit(
2569 if (rex != 0x40) *p++ = rex;
2906 /* Need REX.W = 1 here, but rexAMode_R does that for us. */
2967 /* note, 8-bit register rex trickyness. Be careful here. */
2999 rex = rexAMode_M( hregAMD64_RBX(), i->Ain.ACAS.addr );
3001 rex = clearWBit(rex);
3003 *p++ = rex; /* this can emit 0x40, which is pointless. oh well. */
3015 rex = rexAMode_M( fake(1), i->Ain.ACAS.addr );
3017 rex = clearWBit(rex);
3018 *p++ = rex;
3086 ensuring that REX.W = 0. */
3101 a rex byte of 0x40, since the mere presence of rex changes
3142 rex = rexAMode_R( vreg2ireg(i->Ain.SseSI2SF.dst),
3145 *p++ = toUChar(i->Ain.SseSI2SF.szS==4 ? clearWBit(rex) : rex);
3154 rex = rexAMode_R( i->Ain.SseSF2SI.dst,
3157 *p++ = toUChar(i->Ain.SseSF2SI.szD==4 ? clearWBit(rex) : rex);
3320 rex = clearWBit(
3325 case Asse_MOV: /*movups*/ XX(rex); XX(0x0F); XX(0x10); break;
3326 case Asse_OR: XX(rex); XX(0x0F); XX(0x56); break;
3327 case Asse_XOR: XX(rex); XX(0x0F); XX(0x57); break;
3328 case Asse_AND: XX(rex); XX(0x0F); XX(0x54); break;
3329 case Asse_ANDN: XX(rex); XX(0x0F); XX(0x55); break;
3330 case Asse_PACKSSD: XX(0x66); XX(rex); XX(0x0F); XX(0x6B); break;
3331 case Asse_PACKSSW: XX(0x66); XX(rex); XX(0x0F); XX(0x63); break;
3332 case Asse_PACKUSW: XX(0x66); XX(rex); XX(0x0F); XX(0x67); break;
3333 case Asse_ADD8: XX(0x66); XX(rex); XX(0x0F); XX(0xFC); break;
3334 case Asse_ADD16: XX(0x66); XX(rex); XX(0x0F); XX(0xFD); break;
3335 case Asse_ADD32: XX(0x66); XX(rex); XX(0x0F); XX(0xFE); break;
3336 case Asse_ADD64: XX(0x66); XX(rex); XX(0x0F); XX(0xD4); break;
3337 case Asse_QADD8S: XX(0x66); XX(rex); XX(0x0F); XX(0xEC); break;
3338 case Asse_QADD16S: XX(0x66); XX(rex); XX(0x0F); XX(0xED); break;
3339 case Asse_QADD8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDC); break;
3340 case Asse_QADD16U: XX(0x66); XX(rex); XX(0x0F); XX(0xDD); break;
3341 case Asse_AVG8U: XX(0x66); XX(rex); XX(0x0F); XX(0xE0); break;
3342 case Asse_AVG16U: XX(0x66); XX(rex); XX(0x0F); XX(0xE3); break;
3343 case Asse_CMPEQ8: XX(0x66); XX(rex); XX(0x0F); XX(0x74); break;
3344 case Asse_CMPEQ16: XX(0x66); XX(rex); XX(0x0F); XX(0x75); break;
3345 case Asse_CMPEQ32: XX(0x66); XX(rex); XX(0x0F); XX(0x76); break;
3346 case Asse_CMPGT8S: XX(0x66); XX(rex); XX(0x0F); XX(0x64); break;
3347 case Asse_CMPGT16S: XX(0x66); XX(rex); XX(0x0F); XX(0x65); break;
3348 case Asse_CMPGT32S: XX(0x66); XX(rex); XX(0x0F); XX(0x66); break;
3349 case Asse_MAX16S: XX(0x66); XX(rex); XX(0x0F); XX(0xEE); break;
3350 case Asse_MAX8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDE); break;
3351 case Asse_MIN16S: XX(0x66); XX(rex); XX(0x0F); XX(0xEA); break;
3352 case Asse_MIN8U: XX(0x66); XX(rex); XX(0x0F); XX(0xDA); break;
3353 case Asse_MULHI16U: XX(0x66); XX(rex); XX(0x0F); XX(0xE4); break;
3354 case Asse_MULHI16S: XX(0x66); XX(rex); XX(0x0F); XX(0xE5); break;
3355 case Asse_MUL16: XX(0x66); XX(rex); XX(0x0F); XX(0xD5); break;
3356 case Asse_SHL16: XX(0x66); XX(rex); XX(0x0F); XX(0xF1); break;
3357 case Asse_SHL32: XX(0x66); XX(rex); XX(0x0F); XX(0xF2); break;
3358 case Asse_SHL64: XX(0x66); XX(rex); XX(0x0F); XX(0xF3); break;
3359 case Asse_SAR16: XX(0x66); XX(rex); XX(0x0F); XX(0xE1); break;
3360 case Asse_SAR32: XX(0x66); XX(rex); XX(0x0F); XX(0xE2); break;
3361 case Asse_SHR16: XX(0x66); XX(rex); XX(0x0F); XX(0xD1); break;
3362 case Asse_SHR32: XX(0x66); XX(rex); XX(0x0F); XX(0xD2); break;
3363 case Asse_SHR64: XX(0x66); XX(rex); XX(0x0F); XX(0xD3); break;
3364 case Asse_SUB8: XX(0x66); XX(rex); XX(0x0F); XX(0xF8); break;
3365 case Asse_SUB16: XX(0x66); XX(rex); XX(0x0F); XX(0xF9); break;
3366 case Asse_SUB32: XX(0x66); XX(rex); XX(0x0F); XX(0xFA); break;
3367 case Asse_SUB64: XX(0x66); XX(rex); XX(0x0F); XX(0xFB); break;
3368 case Asse_QSUB8S: XX(0x66); XX(rex); XX(0x0F); XX(0xE8); break;
3369 case Asse_QSUB16S: XX(0x66); XX(rex); XX(0x0F); XX(0xE9); break;
3370 case Asse_QSUB8U: XX(0x66); XX(rex); XX(0x0F); XX(0xD8); break;
3371 case Asse_QSUB16U: XX(0x66); XX(rex); XX(0x0F); XX(0xD9); break;
3372 case Asse_UNPCKHB: XX(0x66); XX(rex); XX(0x0F); XX(0x68); break;
3373 case Asse_UNPCKHW: XX(0x66); XX(rex); XX(0x0F); XX(0x69); break;
3374 case Asse_UNPCKHD: XX(0x66); XX(rex); XX(0x0F); XX(0x6A); break;
3375 case Asse_UNPCKHQ: XX(0x66); XX(rex); XX(0x0F); XX(0x6D); break;
3376 case Asse_UNPCKLB: XX(0x66); XX(rex); XX(0x0F); XX(0x60); break;
3377 case Asse_UNPCKLW: XX(0x66); XX(rex); XX(0x0F); XX(0x61); break;
3378 case Asse_UNPCKLD: XX(0x66); XX(rex); XX(0x0F); XX(0x62); break;
3379 case Asse_UNPCKLQ: XX(0x66); XX(rex); XX(0x0F); XX(0x6C); break;
3443 /* Need to compute the REX byte for the decl in order to prove
3449 rex = clearWBit(rexAMode_M(fake(1), i->Ain.EvCheck.amCounter));
3450 if (rex != 0x40) goto bad; /* We don't expect to need the REX byte. */
3459 /* Once again, verify we don't need REX. The encoding is FF /4.
3460 We don't need REX.W since by default FF /4 in 64-bit mode
3462 rex = clearWBit(rexAMode_M(fake(4), i->Ain.EvCheck.amFailAddr));
3463 if (rex != 0x40) goto bad;
