Lines Matching defs:argR
1124 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
1126 addInstr(env, AMD64Instr_MovxLQ(False, argR, argR));
1128 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RSI()) );
1322 IRExpr* argR = e->Iex.Unop.arg->Iex.Binop.arg2;
1337 AMD64RMI* rmi = iselIntExpr_RMI(env, argR);
2582 HReg argR = iselDblExpr(env, triop->arg3);
2586 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
3072 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3075 addInstr(env, AMD64Instr_Sse32Fx4(op, argR, dst));
3092 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3095 addInstr(env, AMD64Instr_Sse64Fx2(op, argR, dst));
3111 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3114 addInstr(env, AMD64Instr_Sse32FLo(op, argR, dst));
3130 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3133 addInstr(env, AMD64Instr_Sse64FLo(op, argR, dst));
3272 HReg argR = iselVecExpr(env, e->Iex.Binop.arg2);
3296 movupd %argR, 0(%rdx)
3300 addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argR,
3323 HReg argR = iselIntExpr_R(env, e->Iex.Binop.arg2);
3348 addInstr(env, mk_iMOVsd_RR(argR, hregAMD64_RDX()));
