Lines Matching defs:rreg
79 HReg rreg;
95 /* Which rreg is this for? */
96 HReg rreg;
106 rreg has the same value as the spill slot for the associated
108 spill store or reload for this rreg. */
130 rreg" is the main beneficiary.
133 associated with any rreg, that entry can be set to INVALID_RREG_NO.
353 HReg rreg, vreg, vregS, vregD;
391 /* The vreg -> rreg map constructed and then applied to each
429 (*ppReg)(rreg_state[z].rreg); \
470 rreg_state[j].rreg = available_real_regs[j];
483 /* --------- Stage 2: compute rreg live ranges. --------- */
507 /* ------ start of SET UP TO COMPUTE RREG LIVE RANGES ------ */
519 each rreg. Sigh. */
529 /* ------ end of SET UP TO COMPUTE RREG LIVE RANGES ------ */
603 /* ------ start of DEAL WITH RREG LIVE RANGES ------ */
613 rreg = reg_usage.hreg[j];
616 if (hregIsVirtual(rreg))
619 /* Furthermore, we're not interested in this rreg unless it's
624 if (available_real_regs[k] == rreg)
641 vex_printf("\nOFFENDING RREG = ");
648 "first event for rreg is Read");
654 vex_printf("\nOFFENDING RREG = ");
661 "first event for rreg is Modify");
675 rreg_lrs_la[rreg_lrs_used].rreg = rreg;
683 /* ------ end of DEAL WITH RREG LIVE RANGES ------ */
689 /* ------ start of FINALISE RREG LIVE RANGES ------ */
712 rreg_lrs_la[rreg_lrs_used].rreg = available_real_regs[j];
727 rreg = rreg_lrs_la[j].rreg;
728 vassert(!hregIsVirtual(rreg));
729 /* rreg is involved in a HLR. Record this info in the array, if
732 if (rreg_state[k].rreg == rreg)
734 vassert(k < n_rregs); /* else rreg was not found in rreg_state?! */
741 ppReg(rreg_state[j].rreg);
764 /* ------ end of FINALISE RREG LIVE RANGES ------ */
777 (*ppReg)(rreg_lrs_la[j].rreg);
784 (*ppReg)(rreg_lrs_db[j].rreg);
893 /* --------- Stage 4: establish rreg preferences --------- */
897 establish which, if any, rreg each vreg would prefer to be in.
955 (*ppReg)(rreg_lrs[j].rreg);
959 /* find the state entry for this rreg */
961 if (rreg_state[k].rreg == rreg_lrs_la[j].rreg)
964 /* and assert that this rreg is marked as unavailable */
980 if (rreg_lrs_la[k].rreg == rreg_state[j].rreg
989 /* Sanity check 3: all vreg-rreg bindings must bind registers
996 vassert(hregClass(rreg_state[j].rreg)
999 vassert(!hregIsVirtual(rreg_state[j].rreg));
1034 the dst to the src's rreg, and that's all. */
1071 /* This rreg has become associated with a different vreg and
1085 mark the associated rreg as free. */
1100 (*ppReg)(rreg_state[j].rreg);
1106 /* ------ Pre-instruction actions for fixed rreg uses ------ */
1110 one of their live ranges. If any such rreg holds a vreg, we
1111 will have to free up the rreg. The simplest solution which
1112 is correct is to spill the rreg.
1115 * Could move it into some other free rreg, if one is available
1118 of rreg HLRs that are known to be sorted by start point
1129 /* rreg_lrs_la[rreg_lrs_la_next].rreg needs to be freed up.
1140 vex_printf("need to free up rreg: ");
1141 (*ppReg)(rreg_lrs_la[rreg_lrs_la_next].rreg);
1145 if (rreg_state[k].rreg == rreg_lrs_la[rreg_lrs_la_next].rreg)
1147 /* If this fails, we don't have an entry for this rreg.
1161 (*genSpill)( &spill1, &spill2, rreg_state[k].rreg,
1194 We also build up the final vreg->rreg mapping to be applied
1284 /* Now we're trying to find a rreg for "vreg". First of all,
1285 if it already has an rreg assigned, we don't need to do
1292 addToHRegRemap(&remap, vreg, rreg_state[k].rreg);
1293 /* If this rreg is written or modified, mark it as different
1303 currently free rreg available, of the correct class. If
1305 rreg for which the next live-range event is as far ahead
1310 || hregClass(rreg_state[k].rreg) != hregClass(vreg))
1331 addToHRegRemap(&remap, vreg, rreg_state[k].rreg);
1342 (*genReload)( &reload1, &reload2, rreg_state[k].rreg,
1349 /* This rreg is read or modified by the instruction.
1377 if (hregClass(rreg_state[k].rreg) != hregClass(vreg))
1388 /* We can choose to spill any rreg satisfying
1410 vassert(hregClass(rreg_state[spillee].rreg) == hregClass(vreg));
1425 (*genSpill)( &spill1, &spill2, rreg_state[spillee].rreg,
1435 rreg. */
1451 (*genReload)( &reload1, &reload2, rreg_state[spillee].rreg,
1458 /* This rreg is read or modified by the instruction.
1470 rreg_state[spillee].rreg. Note that in the map. */
1471 addToHRegRemap(&remap, vreg, rreg_state[spillee].rreg);
1478 - a suitable vreg->rreg mapping for this instruction has been
1496 /* ------ Post-instruction actions for fixed rreg uses ------ */
1508 /* rreg_lrs_db[[rreg_lrs_db_next].rreg is exiting a hard live
1511 if (rreg_state[k].rreg == rreg_lrs_db[rreg_lrs_db_next].rreg)
1514 this rreg. Which we should. */
1541 vassert(rreg_state[j].rreg == available_real_regs[j]);
