Lines Matching refs:MIPSInstr_Alu
192 addInstr(env, MIPSInstr_Alu(Malu_ADD, sp, sp, MIPSRH_Imm(True,
200 addInstr(env, MIPSInstr_Alu(Malu_SUB, sp, sp,
274 addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
275 addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp, MIPSRH_Imm(False, 3)));
312 return MIPSInstr_Alu(Malu_OR, r_dst, r_src, MIPSRH_Reg(r_src));
719 addInstr(env, MIPSInstr_Alu(aluOp, r_dst, r_srcL, ri_srcR));
858 addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp, argL, argR));
901 addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
904 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
934 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS,
941 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS,
949 addInstr(env, MIPSInstr_Alu(Malu_NOR, tmp, tmp, MIPSRH_Reg(tmp)));
950 addInstr(env, MIPSInstr_Alu(Malu_AND, tmp, tmp,
952 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccMIPS, r_ccMIPS,
968 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR_b0, r_ccMIPS,
970 addInstr(env, MIPSInstr_Alu(Malu_AND, r_ccIR_b0, r_ccIR_b0,
976 addInstr(env, MIPSInstr_Alu(Malu_AND, r_ccIR_b2, r_ccIR_b2,
982 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR_b6, r_ccMIPS,
986 addInstr(env, MIPSInstr_Alu(Malu_AND, r_ccIR_b6, r_ccIR_b6,
990 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR, r_ccIR_b0,
992 addInstr(env, MIPSInstr_Alu(Malu_OR, r_ccIR, r_ccIR,
1018 addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
1021 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
1040 addInstr(env, MIPSInstr_Alu(Malu_AND, tLo_1, tLo,
1042 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, tHi_1,
1132 addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, r_dst, r_srcR));
1142 addInstr(env, MIPSInstr_Alu(Malu_NOR, r_dst, r_srcL, r_srcR));
1192 addInstr(env, MIPSInstr_Alu(Malu_AND, r_dst, r_src,
1233 addInstr(env, MIPSInstr_Alu(Malu_AND, r_dst, r_src,
1289 addInstr(env, MIPSInstr_Alu(Malu_AND, tmp, r_src,
1313 addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, hregMIPS_GPR0(mode64),
1316 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, r_dst,
1330 addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, hregMIPS_GPR0(mode64),
1332 addInstr(env, MIPSInstr_Alu(Malu_OR, r_dst, r_dst,
1350 addInstr(env, MIPSInstr_Alu(Malu_OR, r_src, lo, MIPSRH_Reg(hi)));
1366 addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, hregMIPS_GPR0(mode64),
1369 addInstr(env, MIPSInstr_Alu(Malu_OR, tmp2, tmp2, MIPSRH_Reg(tmp1)));
1429 addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp, r_cond, MIPSRH_Reg(rX)));
1430 addInstr(env, MIPSInstr_Alu(Malu_NOR, r_cond_neg, r_cond,
1432 addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp1, r_cond_neg,
1434 addInstr(env, MIPSInstr_Alu(Malu_ADD, r_dst, r_tmp,
1717 addInstr(env, MIPSInstr_Alu(Malu_SUB, r_dst, r_dst, r_srcR));
1947 addInstr(env, MIPSInstr_Alu(Malu_AND, tmpLo, r_cond,
1949 addInstr(env, MIPSInstr_Alu(Malu_AND, tmpHi, r_cond,
1951 addInstr(env, MIPSInstr_Alu(Malu_NOR, r_cond_neg, r_cond,
1953 addInstr(env, MIPSInstr_Alu(Malu_AND, tmp1Lo, r_cond_neg,
1955 addInstr(env, MIPSInstr_Alu(Malu_AND, tmp1Hi, r_cond_neg,
1957 addInstr(env, MIPSInstr_Alu(Malu_ADD, desLo, tmpLo,
1959 addInstr(env, MIPSInstr_Alu(Malu_ADD, desHi, tmpHi,
1978 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, xHi, MIPSRH_Reg(yHi)));
1979 addInstr(env, MIPSInstr_Alu(Malu_ADD, tLo, xLo, MIPSRH_Reg(yLo)));
2038 addInstr(env, MIPSInstr_Alu(op, tHi, xHi, MIPSRH_Reg(yHi)));
2039 addInstr(env, MIPSInstr_Alu(op, tLo, xLo, MIPSRH_Reg(yLo)));
2093 addInstr(env, MIPSInstr_Alu(Malu_ADD, tHi, hregMIPS_GPR0(mode64),
2107 addInstr(env, MIPSInstr_Alu(Malu_OR, tmp1, srcLo,
2111 addInstr(env, MIPSInstr_Alu(Malu_SUB, tmp2, hregMIPS_GPR0(mode64),
2114 addInstr(env, MIPSInstr_Alu(Malu_OR, tmp2, tmp2, MIPSRH_Reg(tmp1)));
2498 addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
2499 addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp,
2555 addInstr(env, MIPSInstr_Alu(Malu_XOR, tmp, irrm, MIPSRH_Reg(tmp)));
2556 addInstr(env, MIPSInstr_Alu(Malu_AND, irrm, tmp,
2685 addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp_lo, r_cond,
2687 addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp_hi, r_cond,
2690 addInstr(env, MIPSInstr_Alu(Malu_NOR, r_cond_neg, r_cond,
2706 addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp1_lo, r_cond_neg,
2708 addInstr(env, MIPSInstr_Alu(Malu_AND, r_tmp1_hi, r_cond_neg,
2711 addInstr(env, MIPSInstr_Alu(Malu_ADD, r_dst_lo, r_tmp_lo,
2713 addInstr(env, MIPSInstr_Alu(Malu_ADD, r_dst_hi, r_tmp_hi,
