Lines Matching refs:mode64
95 HReg hregPPC_GPR0 ( Bool mode64 ) { return MkHRegGPR( 0, mode64); }
96 HReg hregPPC_GPR1 ( Bool mode64 ) { return MkHRegGPR( 1, mode64); }
97 HReg hregPPC_GPR2 ( Bool mode64 ) { return MkHRegGPR( 2, mode64); }
98 HReg hregPPC_GPR3 ( Bool mode64 ) { return MkHRegGPR( 3, mode64); }
99 HReg hregPPC_GPR4 ( Bool mode64 ) { return MkHRegGPR( 4, mode64); }
100 HReg hregPPC_GPR5 ( Bool mode64 ) { return MkHRegGPR( 5, mode64); }
101 HReg hregPPC_GPR6 ( Bool mode64 ) { return MkHRegGPR( 6, mode64); }
102 HReg hregPPC_GPR7 ( Bool mode64 ) { return MkHRegGPR( 7, mode64); }
103 HReg hregPPC_GPR8 ( Bool mode64 ) { return MkHRegGPR( 8, mode64); }
104 HReg hregPPC_GPR9 ( Bool mode64 ) { return MkHRegGPR( 9, mode64); }
105 HReg hregPPC_GPR10 ( Bool mode64 ) { return MkHRegGPR(10, mode64); }
106 HReg hregPPC_GPR11 ( Bool mode64 ) { return MkHRegGPR(11, mode64); }
107 HReg hregPPC_GPR12 ( Bool mode64 ) { return MkHRegGPR(12, mode64); }
108 HReg hregPPC_GPR13 ( Bool mode64 ) { return MkHRegGPR(13, mode64); }
109 HReg hregPPC_GPR14 ( Bool mode64 ) { return MkHRegGPR(14, mode64); }
110 HReg hregPPC_GPR15 ( Bool mode64 ) { return MkHRegGPR(15, mode64); }
111 HReg hregPPC_GPR16 ( Bool mode64 ) { return MkHRegGPR(16, mode64); }
112 HReg hregPPC_GPR17 ( Bool mode64 ) { return MkHRegGPR(17, mode64); }
113 HReg hregPPC_GPR18 ( Bool mode64 ) { return MkHRegGPR(18, mode64); }
114 HReg hregPPC_GPR19 ( Bool mode64 ) { return MkHRegGPR(19, mode64); }
115 HReg hregPPC_GPR20 ( Bool mode64 ) { return MkHRegGPR(20, mode64); }
116 HReg hregPPC_GPR21 ( Bool mode64 ) { return MkHRegGPR(21, mode64); }
117 HReg hregPPC_GPR22 ( Bool mode64 ) { return MkHRegGPR(22, mode64); }
118 HReg hregPPC_GPR23 ( Bool mode64 ) { return MkHRegGPR(23, mode64); }
119 HReg hregPPC_GPR24 ( Bool mode64 ) { return MkHRegGPR(24, mode64); }
120 HReg hregPPC_GPR25 ( Bool mode64 ) { return MkHRegGPR(25, mode64); }
121 HReg hregPPC_GPR26 ( Bool mode64 ) { return MkHRegGPR(26, mode64); }
122 HReg hregPPC_GPR27 ( Bool mode64 ) { return MkHRegGPR(27, mode64); }
123 HReg hregPPC_GPR28 ( Bool mode64 ) { return MkHRegGPR(28, mode64); }
124 HReg hregPPC_GPR29 ( Bool mode64 ) { return MkHRegGPR(29, mode64); }
125 HReg hregPPC_GPR30 ( Bool mode64 ) { return MkHRegGPR(30, mode64); }
126 HReg hregPPC_GPR31 ( Bool mode64 ) { return MkHRegGPR(31, mode64); }
196 void getAllocableRegs_PPC ( Int* nregs, HReg** arr, Bool mode64 )
199 if (mode64)
207 (*arr)[i++] = hregPPC_GPR3(mode64);
208 (*arr)[i++] = hregPPC_GPR4(mode64);
209 (*arr)[i++] = hregPPC_GPR5(mode64);
210 (*arr)[i++] = hregPPC_GPR6(mode64);
211 (*arr)[i++] = hregPPC_GPR7(mode64);
212 (*arr)[i++] = hregPPC_GPR8(mode64);
213 (*arr)[i++] = hregPPC_GPR9(mode64);
214 (*arr)[i++] = hregPPC_GPR10(mode64);
215 if (!mode64) {
216 /* in mode64:
219 (*arr)[i++] = hregPPC_GPR11(mode64);
220 (*arr)[i++] = hregPPC_GPR12(mode64);
224 (*arr)[i++] = hregPPC_GPR14(mode64);
225 (*arr)[i++] = hregPPC_GPR15(mode64);
226 (*arr)[i++] = hregPPC_GPR16(mode64);
227 (*arr)[i++] = hregPPC_GPR17(mode64);
228 (*arr)[i++] = hregPPC_GPR18(mode64);
229 (*arr)[i++] = hregPPC_GPR19(mode64);
230 (*arr)[i++] = hregPPC_GPR20(mode64);
231 (*arr)[i++] = hregPPC_GPR21(mode64);
232 (*arr)[i++] = hregPPC_GPR22(mode64);
233 (*arr)[i++] = hregPPC_GPR23(mode64);
234 (*arr)[i++] = hregPPC_GPR24(mode64);
235 (*arr)[i++] = hregPPC_GPR25(mode64);
236 (*arr)[i++] = hregPPC_GPR26(mode64);
237 (*arr)[i++] = hregPPC_GPR27(mode64);
238 (*arr)[i++] = hregPPC_GPR28(mode64);
753 PPCInstr* PPCInstr_LI ( HReg dst, ULong imm64, Bool mode64 )
759 if (!mode64)
894 HReg dst, PPCAMode* src, Bool mode64 ) {
901 if (sz == 8) vassert(mode64);
905 HReg dst, HReg src, Bool mode64 )
913 if (sz == 8) vassert(mode64);
917 Bool mode64 ) {
924 if (sz == 8) vassert(mode64);
927 PPCInstr* PPCInstr_StoreC ( UChar sz, HReg dst, HReg src, Bool mode64 ) {
934 if (sz == 8) vassert(mode64);
1421 static void ppLoadImm ( HReg dst, ULong imm, Bool mode64 ) {
1424 if (!mode64) {
1440 void ppPPCInstr ( PPCInstr* i, Bool mode64 )
1444 ppLoadImm(i->Pin.LI.dst, i->Pin.LI.imm64, mode64);
1547 ppLoadImm(hregPPC_GPR10(mode64), i->Pin.Call.target, mode64);
1563 if (mode64) {
1572 if (mode64) {
1585 vex_printf("%s ", mode64 ? "std" : "stw");
1590 vex_printf("imm%s r30,$disp_cp_xindir; ", mode64 ? "64" : "32");
1597 vex_printf("%s ", mode64 ? "std" : "stw");
1604 vex_printf("imm%s r30,$disp_cp_xindir; ", mode64 ? "64" : "32");
1618 ppLoadImm(i->Pin.CMov.dst, i->Pin.CMov.src->Pri.Imm, mode64);
1825 ppLoadImm(hregPPC_GPR30(mode64),
1826 i->Pin.AvLdSt.addr->Pam.RR.index, mode64);
2122 if (mode64) {
2139 void getRegUsage_PPCInstr ( HRegUsage* u, PPCInstr* i, Bool mode64 )
2186 mode64: r3 to r10
2192 addHRegUse(u, HRmWrite, hregPPC_GPR3(mode64));
2193 addHRegUse(u, HRmWrite, hregPPC_GPR4(mode64));
2194 addHRegUse(u, HRmWrite, hregPPC_GPR5(mode64));
2195 addHRegUse(u, HRmWrite, hregPPC_GPR6(mode64));
2196 addHRegUse(u, HRmWrite, hregPPC_GPR7(mode64));
2197 addHRegUse(u, HRmWrite, hregPPC_GPR8(mode64));
2198 addHRegUse(u, HRmWrite, hregPPC_GPR9(mode64));
2199 addHRegUse(u, HRmWrite, hregPPC_GPR10(mode64));
2200 if (!mode64) {
2201 addHRegUse(u, HRmWrite, hregPPC_GPR11(mode64));
2202 addHRegUse(u, HRmWrite, hregPPC_GPR12(mode64));
2208 if (argir &(1<<10)) addHRegUse(u, HRmRead, hregPPC_GPR10(mode64));
2209 if (argir & (1<<9)) addHRegUse(u, HRmRead, hregPPC_GPR9(mode64));
2210 if (argir & (1<<8)) addHRegUse(u, HRmRead, hregPPC_GPR8(mode64));
2211 if (argir & (1<<7)) addHRegUse(u, HRmRead, hregPPC_GPR7(mode64));
2212 if (argir & (1<<6)) addHRegUse(u, HRmRead, hregPPC_GPR6(mode64));
2213 if (argir & (1<<5)) addHRegUse(u, HRmRead, hregPPC_GPR5(mode64));
2214 if (argir & (1<<4)) addHRegUse(u, HRmRead, hregPPC_GPR4(mode64));
2215 if (argir & (1<<3)) addHRegUse(u, HRmRead, hregPPC_GPR3(mode64));
2224 addHRegUse(u, HRmWrite, hregPPC_GPR10(mode64));
2328 addHRegUse(u, HRmWrite, hregPPC_GPR30(mode64));
2497 addHRegUse(u, HRmWrite, hregPPC_GPR30(mode64)); /* also unavail to RA */
2500 addHRegUse(u, HRmWrite, hregPPC_GPR29(mode64));
2501 addHRegUse(u, HRmWrite, hregPPC_GPR30(mode64));
2504 ppPPCInstr(i, mode64);
2515 void mapRegs_PPCInstr ( HRegRemap* m, PPCInstr* i, Bool mode64 )
2807 ppPPCInstr(i, mode64);
2848 HReg rreg, Int offsetB, Bool mode64 )
2853 am = PPCAMode_IR( offsetB, GuestStatePtr(mode64) );
2856 vassert(mode64);
2857 *i1 = PPCInstr_Store( 8, am, rreg, mode64 );
2860 vassert(!mode64);
2861 *i1 = PPCInstr_Store( 4, am, rreg, mode64 );
2878 HReg rreg, Int offsetB, Bool mode64 )
2883 mode64) );
2886 vassert(mode64);
2887 *i1 = PPCInstr_Load( 8, rreg, am, mode64 );
2890 vassert(!mode64);
2891 *i1 = PPCInstr_Load( 4, rreg, am, mode64 );
2909 static UInt iregNo ( HReg r, Bool mode64 )
2912 vassert(hregClass(r) == mode64 ? HRcInt64 : HRcInt32);
3183 PPCAMode* am, Bool mode64 )
3189 rA = iregNo(am->Pam.IR.base, mode64);
3192 if (opc1 == 58 || opc1 == 62) { // ld/std: mode64 only
3193 vassert(mode64);
3203 UInt rSD, PPCAMode* am, Bool mode64 )
3208 rA = iregNo(am->Pam.RR.base, mode64);
3209 rB = iregNo(am->Pam.RR.index, mode64);
3217 static UChar* mkLoadImm ( UChar* p, UInt r_dst, ULong imm, Bool mode64 )
3221 if (!mode64) {
3246 vassert(mode64);
3279 UInt r_dst, ULong imm, Bool mode64 )
3283 if (!mode64) {
3292 if (!mode64) {
3324 UInt r_dst, ULong imm, Bool mode64 )
3328 if (!mode64) {
3337 if (!mode64) {
3386 UInt reg, PPCAMode* am, Bool mode64 )
3389 UInt opc1, sz = mode64 ? 8 : 4;
3392 if (mode64) {
3396 case 4: opc1 = 32; vassert(!mode64); break;
3397 case 8: opc1 = 58; vassert(mode64); break;
3400 p = doAMode_IR(p, opc1, reg, am, mode64);
3410 UInt opc1, sz = mode64 ? 8 : 4;
3413 if (mode64) {
3417 case 4: opc1 = 36; vassert(!mode64); break;
3418 case 8: opc1 = 62; vassert(mode64); break;
3421 p = doAMode_IR(p, opc1, reg, am, mode64);
3438 UInt reg, PPCAMode* am, Bool mode64 )
3444 if (mode64) {
3448 p = doAMode_IR(p, opc1, reg, am, mode64);
3461 if (mode64) {
3465 p = doAMode_IR(p, opc1, reg, am, mode64);
3544 Bool mode64,
3554 vex_printf("asm ");ppPPCInstr(i, mode64); vex_printf("\n");
3560 p = mkLoadImm(p, iregNo(i->Pin.LI.dst, mode64),
3561 i->Pin.LI.imm64, mode64);
3567 UInt r_dst = iregNo(i->Pin.Alu.dst, mode64);
3568 UInt r_srcL = iregNo(i->Pin.Alu.srcL, mode64);
3570 iregNo(srcR->Prh.Reg.reg, mode64);
3640 UInt r_dst = iregNo(i->Pin.Shft.dst, mode64);
3641 UInt r_srcL = iregNo(i->Pin.Shft.srcL, mode64);
3643 iregNo(srcR->Prh.Reg.reg, mode64);
3644 if (!mode64)
3721 if (mode64)
3753 UInt r_srcL = iregNo(i->Pin.AddSubC.srcL, mode64);
3754 UInt r_srcR = iregNo(i->Pin.AddSubC.srcR, mode64);
3755 UInt r_dst = iregNo(i->Pin.AddSubC.dst, mode64);
3776 UInt r_srcL = iregNo(i->Pin.Cmp.srcL, mode64);
3780 if (!mode64) // cmp double word invalid for mode32
3782 else if (!sz32) // mode64 && cmp64: set L=1
3797 r_srcR = iregNo(srcR->Prh.Reg.reg, mode64);
3810 UInt r_dst = iregNo(i->Pin.Unary.dst, mode64);
3811 UInt r_src = iregNo(i->Pin.Unary.src, mode64);
3824 vassert(mode64);
3828 vassert(mode64);
3839 UInt r_dst = iregNo(i->Pin.MulL.dst, mode64);
3840 UInt r_srcL = iregNo(i->Pin.MulL.srcL, mode64);
3841 UInt r_srcR = iregNo(i->Pin.MulL.srcR, mode64);
3843 if (!mode64)
3873 UInt r_dst = iregNo(i->Pin.Div.dst, mode64);
3874 UInt r_srcL = iregNo(i->Pin.Div.srcL, mode64);
3875 UInt r_srcR = iregNo(i->Pin.Div.srcR, mode64);
3877 if (!mode64)
3927 p = mkLoadImm(p, r_dst, i->Pin.Call.target, mode64);
3969 if (!mode64) vassert(0 == (((ULong)i->Pin.XDirect.dstGA) >> 32));
3970 p = mkLoadImm(p, /*r*/30, (ULong)i->Pin.XDirect.dstGA, mode64);
3974 /*r*/30, i->Pin.XDirect.amCIA, mode64
3987 p, /*r*/30, Ptr_to_ULong(disp_cp_chain_me), mode64);
4030 iregNo(i->Pin.XIndir.dstGA, mode64),
4031 i->Pin.XIndir.amCIA, mode64
4035 p = mkLoadImm(p, /*r*/30, (ULong)Ptr_to_ULong(disp_cp_xindir), mode64);
4069 iregNo(i->Pin.XIndir.dstGA, mode64),
4070 i->Pin.XIndir.amCIA, mode64
4099 p = mkLoadImm(p, /*r*/31, trcval, mode64);
4103 (ULong)Ptr_to_ULong(disp_cp_xassisted), mode64);
4126 r_dst = iregNo(i->Pin.CMov.dst, mode64);
4142 p = mkLoadImm(p, r_dst, imm_src, mode64); // p += 4|8|20
4145 r_src = iregNo(i->Pin.CMov.src->Pri.Reg, mode64);
4164 UInt r_dst = iregNo(i->Pin.Load.dst, mode64);
4168 if (mode64 && (sz == 4 || sz == 8)) {
4176 case 8: opc1 = 58; vassert(mode64); break;
4179 p = doAMode_IR(p, opc1, r_dst, am_addr, mode64);
4186 case 8: opc2 = 21; vassert(mode64); break;
4189 p = doAMode_RR(p, 31, opc2, r_dst, am_addr, mode64);
4198 p = mkFormX(p, 31, iregNo(i->Pin.LoadL.dst, mode64),
4199 0, iregNo(i->Pin.LoadL.src, mode64), 20, 0);
4202 if (i->Pin.LoadL.sz == 8 && mode64) {
4203 p = mkFormX(p, 31, iregNo(i->Pin.LoadL.dst, mode64),
4204 0, iregNo(i->Pin.LoadL.src, mode64), 84, 0);
4213 UInt r_dst = iregNo(i->Pin.Set.dst, mode64);
4242 p = mkFormX(p, 31, iregNo(i->Pin.MfCR.dst, mode64), 0, 0, 19, 0);
4254 UInt r_src = iregNo(i->Pin.Store.src, mode64);
4258 if (mode64 && (sz == 4 || sz == 8)) {
4266 case 8: vassert(mode64);
4271 p = doAMode_IR(p, opc1, r_src, am_addr, mode64);
4278 case 8: vassert(mode64);
4283 p = doAMode_RR(p, 31, opc2, r_src, am_addr, mode64);
4293 p = mkFormX(p, 31, iregNo(i->Pin.StoreC.src, mode64),
4294 0, iregNo(i->Pin.StoreC.dst, mode64), 150, 1);
4297 if (i->Pin.StoreC.sz == 8 && mode64) {
4298 p = mkFormX(p, 31, iregNo(i->Pin.StoreC.src, mode64),
4299 0, iregNo(i->Pin.StoreC.dst, mode64), 214, 1);
4415 p = doAMode_RR(p, 31, opc, f_reg, am_addr, mode64);
4418 p = doAMode_IR(p, opc, f_reg, am_addr, mode64);
4423 p = doAMode_RR(p, 31, opc, f_reg, am_addr, mode64);
4426 p = doAMode_IR(p, opc, f_reg, am_addr, mode64);
4433 UInt ir_addr = iregNo(i->Pin.FpSTFIW.addr, mode64);
4520 UInt r_dst = iregNo(i->Pin.FpCmp.dst, mode64);
4537 UInt reg = iregNo(i->Pin.RdWrLR.gpr, mode64);
4552 r_base = iregNo(i->Pin.AvLdSt.addr->Pam.RR.base, mode64);
4558 i->Pin.AvLdSt.addr->Pam.IR.index, mode64);
4560 r_idx = iregNo(i->Pin.AvLdSt.addr->Pam.RR.index, mode64);
5333 UInt r_dst = iregNo(i->Pin.Dfp64Cmp.dst, mode64);
5351 UInt r_dst = iregNo(i->Pin.Dfp128Cmp.dst, mode64);
5393 i->Pin.EvCheck.amCounter, mode64);
5398 i->Pin.EvCheck.amCounter, mode64);
5403 i->Pin.EvCheck.amFailAddr, mode64);
5435 if (mode64) {
5437 p, /*r*/30, 0x6555655565556555ULL, True/*mode64*/);
5443 p, /*r*/30, 0x65556555ULL, False/*!mode64*/);
5463 ppPPCInstr(i, mode64);
5487 Bool mode64 )
5502 mode64));
5503 vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x7FC903A6);
5504 vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x4E800421);
5516 Ptr_to_ULong(place_to_jump_to), mode64);
5521 vassert(len == (mode64 ? 28 : 16)); /* stay sane */
5532 Bool mode64 )
5547 mode64));
5548 vassert(fetch32(p + (mode64 ? 20 : 8) + 0) == 0x7FC903A6);
5549 vassert(fetch32(p + (mode64 ? 20 : 8) + 4) == 0x4E800420);
5561 Ptr_to_ULong(disp_cp_chain_me), mode64);
5566 vassert(len == (mode64 ? 28 : 16)); /* stay sane */
5576 Bool mode64 )
5582 if (mode64) {
5584 0x6555655565556555ULL, True/*mode64*/));
5590 True/*mode64*/);
5595 0x65556555ULL, False/*!mode64*/));
5604 False/*!mode64*/);
