Lines Matching defs:info
41 // All CPUID info taken from sandpile.org/ia32/cpuid.htm */
68 UChar info[16];
71 /* If we see L3 cache info, copy it into L3c. Then, at the end,
76 info[]. */
91 VG_(cpuid)(2, 0, (Int*)&info[0], (Int*)&info[4],
92 (Int*)&info[8], (Int*)&info[12]);
93 trials = info[0] - 1; /* AL register - bits 0..7 of %eax */
94 info[0] = 0x0; /* reset AL */
104 switch (info[i]) {
109 /* TLB info, ignore */
132 /* IA-64 info -- panic! */
138 /* L3 cache info. */
245 VG_(cpuid)(4, j++, (Int*)&info[0], (Int*)&info[4],
246 (Int*)&info[8], (Int*)&info[12]);
248 while ((info[0] & 0x1f) != 0) {
249 UInt assoc = ((*(UInt *)&info[4] >> 22) & 0x3ff) + 1;
250 UInt parts = ((*(UInt *)&info[4] >> 12) & 0x3ff) + 1;
251 UInt line_size = (*(UInt *)&info[4] & 0x7ff) + 1;
252 UInt sets = *(UInt *)&info[8] + 1;
259 switch ((info[0] & 0xe0) >> 5)
262 switch (info[0] & 0x1f)
271 switch (info[0] & 0x1f)
280 switch (info[0] & 0x1f)
289 VG_(dmsg)("warning: L%u cache ignored\n", (info[0] & 0xe0) >> 5);
293 VG_(cpuid)(4, j++, (Int*)&info[0], (Int*)&info[4],
294 (Int*)&info[8], (Int*)&info[12]);
300 info[i]);
404 /* There's an L3 cache. Replace *LLc contents with this info. */
534 // Then replace with any info we can get from CPUID.
