Lines Matching refs:Miss
42 - one block hits, the other misses --> one miss
43 - both blocks miss --> one miss (not two)
133 typedef enum { Hit = 0, Miss, MissDirty } CacheResult;
268 /* A miss; install this tag as MRU, shuffle rest down. */
274 return Miss;
295 return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit;
336 * With write-back, result can be a miss evicting a dirty line
369 /* A miss; install this tag as MRU, shuffle rest down. */
376 return (tmp_tag & CACHELINE_DIRTY) ? MissDirty : Miss;
401 return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit;
417 case Miss: return MemAccess;
429 case Miss: return MemAccess;
448 case Miss: return MemAccess;
546 case Miss: return MemAccess;
559 case Miss: return MemAccess;
579 case Miss: return MemAccess;
726 /* A miss; install this tag as MRU, shuffle rest down. */ \
739 Int miss1=0, miss2=0; /* 0: L1 hit, 1:L1 miss, 2:LL miss */ \
846 CLG_DEBUG(2, " LL.miss [%d]: at %#lx accessing memline %#lx\n",
908 /* A miss; install this tag as MRU, shuffle rest down. */
934 CLG_DEBUG(2, " %s.miss [%d]: at %#lx accessing memline %#lx (mask %08x)\n", \
1042 case MemAccess: return "LL Miss";
1043 case WriteBackMemAccess: return "LL Miss (dirty)";
1552 VG_(message)(Vg_UserMsg, "I1 miss rate: %s\n", buf1);
1556 VG_(message)(Vg_UserMsg, "LLi miss rate: %s\n", buf1);
1598 VG_(message)(Vg_UserMsg, "D1 miss rate: %s (%s + %s )\n",
1606 VG_(message)(Vg_UserMsg, "LLd miss rate: %s (%s + %s )\n",
1649 VG_(message)(Vg_UserMsg, "LL miss rate: %s (%s + %s )\n",
