Home | History | Annotate | Download | only in X86 
      1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file implements the X86 specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #define DEBUG_TYPE "subtarget"
     15 #include "X86Subtarget.h"
     16 #include "X86InstrInfo.h"
     17 #include "llvm/IR/Attributes.h"
     18 #include "llvm/IR/Function.h"
     19 #include "llvm/IR/GlobalValue.h"
     20 #include "llvm/Support/Debug.h"
     21 #include "llvm/Support/ErrorHandling.h"
     22 #include "llvm/Support/Host.h"
     23 #include "llvm/Support/raw_ostream.h"
     24 #include "llvm/Target/TargetMachine.h"
     25 #include "llvm/Target/TargetOptions.h"
     26 
     27 #define GET_SUBTARGETINFO_TARGET_DESC
     28 #define GET_SUBTARGETINFO_CTOR
     29 #include "X86GenSubtargetInfo.inc"
     30 
     31 using namespace llvm;
     32 
     33 #if defined(_MSC_VER)
     34 #include <intrin.h>
     35 #endif
     36 
     37 /// ClassifyBlockAddressReference - Classify a blockaddress reference for the
     38 /// current subtarget according to how we should reference it in a non-pcrel
     39 /// context.
     40 unsigned char X86Subtarget::ClassifyBlockAddressReference() const {
     41   if (isPICStyleGOT())    // 32-bit ELF targets.
     42     return X86II::MO_GOTOFF;
     43 
     44   if (isPICStyleStubPIC())   // Darwin/32 in PIC mode.
     45     return X86II::MO_PIC_BASE_OFFSET;
     46 
     47   // Direct static reference to label.
     48   return X86II::MO_NO_FLAG;
     49 }
     50 
     51 /// ClassifyGlobalReference - Classify a global variable reference for the
     52 /// current subtarget according to how we should reference it in a non-pcrel
     53 /// context.
     54 unsigned char X86Subtarget::
     55 ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const {
     56   // DLLImport only exists on windows, it is implemented as a load from a
     57   // DLLIMPORT stub.
     58   if (GV->hasDLLImportLinkage())
     59     return X86II::MO_DLLIMPORT;
     60 
     61   // Determine whether this is a reference to a definition or a declaration.
     62   // Materializable GVs (in JIT lazy compilation mode) do not require an extra
     63   // load from stub.
     64   bool isDecl = GV->hasAvailableExternallyLinkage();
     65   if (GV->isDeclaration() && !GV->isMaterializable())
     66     isDecl = true;
     67 
     68   // X86-64 in PIC mode.
     69   if (isPICStyleRIPRel()) {
     70     // Large model never uses stubs.
     71     if (TM.getCodeModel() == CodeModel::Large)
     72       return X86II::MO_NO_FLAG;
     73 
     74     if (isTargetDarwin()) {
     75       // If symbol visibility is hidden, the extra load is not needed if
     76       // target is x86-64 or the symbol is definitely defined in the current
     77       // translation unit.
     78       if (GV->hasDefaultVisibility() &&
     79           (isDecl || GV->isWeakForLinker()))
     80         return X86II::MO_GOTPCREL;
     81     } else if (!isTargetWin64()) {
     82       assert(isTargetELF() && "Unknown rip-relative target");
     83 
     84       // Extra load is needed for all externally visible.
     85       if (!GV->hasLocalLinkage() && GV->hasDefaultVisibility())
     86         return X86II::MO_GOTPCREL;
     87     }
     88 
     89     return X86II::MO_NO_FLAG;
     90   }
     91 
     92   if (isPICStyleGOT()) {   // 32-bit ELF targets.
     93     // Extra load is needed for all externally visible.
     94     if (GV->hasLocalLinkage() || GV->hasHiddenVisibility())
     95       return X86II::MO_GOTOFF;
     96     return X86II::MO_GOT;
     97   }
     98 
     99   if (isPICStyleStubPIC()) {  // Darwin/32 in PIC mode.
    100     // Determine whether we have a stub reference and/or whether the reference
    101     // is relative to the PIC base or not.
    102 
    103     // If this is a strong reference to a definition, it is definitely not
    104     // through a stub.
    105     if (!isDecl && !GV->isWeakForLinker())
    106       return X86II::MO_PIC_BASE_OFFSET;
    107 
    108     // Unless we have a symbol with hidden visibility, we have to go through a
    109     // normal $non_lazy_ptr stub because this symbol might be resolved late.
    110     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
    111       return X86II::MO_DARWIN_NONLAZY_PIC_BASE;
    112 
    113     // If symbol visibility is hidden, we have a stub for common symbol
    114     // references and external declarations.
    115     if (isDecl || GV->hasCommonLinkage()) {
    116       // Hidden $non_lazy_ptr reference.
    117       return X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE;
    118     }
    119 
    120     // Otherwise, no stub.
    121     return X86II::MO_PIC_BASE_OFFSET;
    122   }
    123 
    124   if (isPICStyleStubNoDynamic()) {  // Darwin/32 in -mdynamic-no-pic mode.
    125     // Determine whether we have a stub reference.
    126 
    127     // If this is a strong reference to a definition, it is definitely not
    128     // through a stub.
    129     if (!isDecl && !GV->isWeakForLinker())
    130       return X86II::MO_NO_FLAG;
    131 
    132     // Unless we have a symbol with hidden visibility, we have to go through a
    133     // normal $non_lazy_ptr stub because this symbol might be resolved late.
    134     if (!GV->hasHiddenVisibility())  // Non-hidden $non_lazy_ptr reference.
    135       return X86II::MO_DARWIN_NONLAZY;
    136 
    137     // Otherwise, no stub.
    138     return X86II::MO_NO_FLAG;
    139   }
    140 
    141   // Direct static reference to global.
    142   return X86II::MO_NO_FLAG;
    143 }
    144 
    145 
    146 /// getBZeroEntry - This function returns the name of a function which has an
    147 /// interface like the non-standard bzero function, if such a function exists on
    148 /// the current subtarget and it is considered prefereable over memset with zero
    149 /// passed as the second argument. Otherwise it returns null.
    150 const char *X86Subtarget::getBZeroEntry() const {
    151   // Darwin 10 has a __bzero entry point for this purpose.
    152   if (getTargetTriple().isMacOSX() &&
    153       !getTargetTriple().isMacOSXVersionLT(10, 6))
    154     return "__bzero";
    155 
    156   return 0;
    157 }
    158 
    159 bool X86Subtarget::hasSinCos() const {
    160   return getTargetTriple().isMacOSX() &&
    161     !getTargetTriple().isMacOSXVersionLT(10, 9) &&
    162     is64Bit();
    163 }
    164 
    165 /// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
    166 /// to immediate address.
    167 bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
    168   if (In64BitMode)
    169     return false;
    170   return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
    171 }
    172 
    173 static bool OSHasAVXSupport() {
    174 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
    175     || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
    176 #if defined(__GNUC__)
    177   // Check xgetbv; this uses a .byte sequence instead of the instruction
    178   // directly because older assemblers do not include support for xgetbv and
    179   // there is no easy way to conditionally compile based on the assembler used.
    180   int rEAX, rEDX;
    181   __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0));
    182 #elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK)
    183   unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK);
    184 #else
    185   int rEAX = 0; // Ensures we return false
    186 #endif
    187   return (rEAX & 6) == 6;
    188 #else
    189   return false;
    190 #endif
    191 }
    192 
    193 void X86Subtarget::AutoDetectSubtargetFeatures() {
    194   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
    195   unsigned MaxLevel;
    196   union {
    197     unsigned u[3];
    198     char     c[12];
    199   } text;
    200 
    201   if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) ||
    202       MaxLevel < 1)
    203     return;
    204 
    205   X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
    206 
    207   if ((EDX >> 15) & 1) { HasCMov = true;      ToggleFeature(X86::FeatureCMOV); }
    208   if ((EDX >> 23) & 1) { X86SSELevel = MMX;   ToggleFeature(X86::FeatureMMX);  }
    209   if ((EDX >> 25) & 1) { X86SSELevel = SSE1;  ToggleFeature(X86::FeatureSSE1); }
    210   if ((EDX >> 26) & 1) { X86SSELevel = SSE2;  ToggleFeature(X86::FeatureSSE2); }
    211   if (ECX & 0x1)       { X86SSELevel = SSE3;  ToggleFeature(X86::FeatureSSE3); }
    212   if ((ECX >> 9)  & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);}
    213   if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);}
    214   if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);}
    215   if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) {
    216     X86SSELevel = AVX;   ToggleFeature(X86::FeatureAVX);
    217   }
    218 
    219   bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0;
    220   bool IsAMD   = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0;
    221 
    222   if ((ECX >> 1) & 0x1) {
    223     HasPCLMUL = true;
    224     ToggleFeature(X86::FeaturePCLMUL);
    225   }
    226   if ((ECX >> 12) & 0x1) {
    227     HasFMA = true;
    228     ToggleFeature(X86::FeatureFMA);
    229   }
    230   if (IsIntel && ((ECX >> 22) & 0x1)) {
    231     HasMOVBE = true;
    232     ToggleFeature(X86::FeatureMOVBE);
    233   }
    234   if ((ECX >> 23) & 0x1) {
    235     HasPOPCNT = true;
    236     ToggleFeature(X86::FeaturePOPCNT);
    237   }
    238   if ((ECX >> 25) & 0x1) {
    239     HasAES = true;
    240     ToggleFeature(X86::FeatureAES);
    241   }
    242   if ((ECX >> 29) & 0x1) {
    243     HasF16C = true;
    244     ToggleFeature(X86::FeatureF16C);
    245   }
    246   if (IsIntel && ((ECX >> 30) & 0x1)) {
    247     HasRDRAND = true;
    248     ToggleFeature(X86::FeatureRDRAND);
    249   }
    250 
    251   if ((ECX >> 13) & 0x1) {
    252     HasCmpxchg16b = true;
    253     ToggleFeature(X86::FeatureCMPXCHG16B);
    254   }
    255 
    256   if (IsIntel || IsAMD) {
    257     // Determine if bit test memory instructions are slow.
    258     unsigned Family = 0;
    259     unsigned Model  = 0;
    260     X86_MC::DetectFamilyModel(EAX, Family, Model);
    261     if (IsAMD || (Family == 6 && Model >= 13)) {
    262       IsBTMemSlow = true;
    263       ToggleFeature(X86::FeatureSlowBTMem);
    264     }
    265 
    266     // If it's an Intel chip since Nehalem and not an Atom chip, unaligned
    267     // memory access is fast. We hard code model numbers here because they
    268     // aren't strictly increasing for Intel chips it seems.
    269     if (IsIntel &&
    270         ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield,
    271                                            //          Jasper Froest
    272          (Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP
    273          (Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX
    274          (Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale
    275          (Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP
    276          (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX
    277          (Family == 6 && Model == 0x2A) || // SandyBridge
    278          (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E*
    279          (Family == 6 && Model == 0x3A))) {// IvyBridge
    280       IsUAMemFast = true;
    281       ToggleFeature(X86::FeatureFastUAMem);
    282     }
    283 
    284     // Set processor type. Currently only Atom is detected.
    285     if (Family == 6 &&
    286         (Model == 28 || Model == 38 || Model == 39
    287          || Model == 53 || Model == 54)) {
    288       X86ProcFamily = IntelAtom;
    289 
    290       UseLeaForSP = true;
    291       ToggleFeature(X86::FeatureLeaForSP);
    292     }
    293 
    294     unsigned MaxExtLevel;
    295     X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
    296 
    297     if (MaxExtLevel >= 0x80000001) {
    298       X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
    299       if ((EDX >> 29) & 0x1) {
    300         HasX86_64 = true;
    301         ToggleFeature(X86::Feature64Bit);
    302       }
    303       if ((ECX >> 5) & 0x1) {
    304         HasLZCNT = true;
    305         ToggleFeature(X86::FeatureLZCNT);
    306       }
    307       if (IsIntel && ((ECX >> 8) & 0x1)) {
    308         HasPRFCHW = true;
    309         ToggleFeature(X86::FeaturePRFCHW);
    310       }
    311       if (IsAMD) {
    312         if ((ECX >> 6) & 0x1) {
    313           HasSSE4A = true;
    314           ToggleFeature(X86::FeatureSSE4A);
    315         }
    316         if ((ECX >> 11) & 0x1) {
    317           HasXOP = true;
    318           ToggleFeature(X86::FeatureXOP);
    319         }
    320         if ((ECX >> 16) & 0x1) {
    321           HasFMA4 = true;
    322           ToggleFeature(X86::FeatureFMA4);
    323         }
    324       }
    325     }
    326   }
    327 
    328   if (MaxLevel >= 7) {
    329     if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) {
    330       if (IsIntel && (EBX & 0x1)) {
    331         HasFSGSBase = true;
    332         ToggleFeature(X86::FeatureFSGSBase);
    333       }
    334       if ((EBX >> 3) & 0x1) {
    335         HasBMI = true;
    336         ToggleFeature(X86::FeatureBMI);
    337       }
    338       if ((EBX >> 4) & 0x1) {
    339         HasHLE = true;
    340         ToggleFeature(X86::FeatureHLE);
    341       }
    342       if (IsIntel && ((EBX >> 5) & 0x1)) {
    343         X86SSELevel = AVX2;
    344         ToggleFeature(X86::FeatureAVX2);
    345       }
    346       if (IsIntel && ((EBX >> 8) & 0x1)) {
    347         HasBMI2 = true;
    348         ToggleFeature(X86::FeatureBMI2);
    349       }
    350       if (IsIntel && ((EBX >> 11) & 0x1)) {
    351         HasRTM = true;
    352         ToggleFeature(X86::FeatureRTM);
    353       }
    354       if (IsIntel && ((EBX >> 19) & 0x1)) {
    355         HasADX = true;
    356         ToggleFeature(X86::FeatureADX);
    357       }
    358       if (IsIntel && ((EBX >> 18) & 0x1)) {
    359         HasRDSEED = true;
    360         ToggleFeature(X86::FeatureRDSEED);
    361       }
    362     }
    363   }
    364 }
    365 
    366 void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) {
    367   AttributeSet FnAttrs = MF->getFunction()->getAttributes();
    368   Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
    369                                            "target-cpu");
    370   Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex,
    371                                           "target-features");
    372   std::string CPU =
    373     !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : "";
    374   std::string FS =
    375     !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : "";
    376   if (!FS.empty()) {
    377     initializeEnvironment();
    378     resetSubtargetFeatures(CPU, FS);
    379   }
    380 }
    381 
    382 void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) {
    383   std::string CPUName = CPU;
    384   if (!FS.empty() || !CPU.empty()) {
    385     if (CPUName.empty()) {
    386 #if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\
    387     || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64)
    388       CPUName = sys::getHostCPUName();
    389 #else
    390       CPUName = "generic";
    391 #endif
    392     }
    393 
    394     // Make sure 64-bit features are available in 64-bit mode. (But make sure
    395     // SSE2 can be turned off explicitly.)
    396     std::string FullFS = FS;
    397     if (In64BitMode) {
    398       if (!FullFS.empty())
    399         FullFS = "+64bit,+sse2," + FullFS;
    400       else
    401         FullFS = "+64bit,+sse2";
    402     }
    403 
    404     // If feature string is not empty, parse features string.
    405     ParseSubtargetFeatures(CPUName, FullFS);
    406   } else {
    407     if (CPUName.empty()) {
    408 #if defined (__x86_64__) || defined(__i386__)
    409       CPUName = sys::getHostCPUName();
    410 #else
    411       CPUName = "generic";
    412 #endif
    413     }
    414     // Otherwise, use CPUID to auto-detect feature set.
    415     AutoDetectSubtargetFeatures();
    416 
    417     // Make sure 64-bit features are available in 64-bit mode.
    418     if (In64BitMode) {
    419       HasX86_64 = true; ToggleFeature(X86::Feature64Bit);
    420       HasCMov = true;   ToggleFeature(X86::FeatureCMOV);
    421 
    422       if (X86SSELevel < SSE2) {
    423         X86SSELevel = SSE2;
    424         ToggleFeature(X86::FeatureSSE1);
    425         ToggleFeature(X86::FeatureSSE2);
    426       }
    427     }
    428   }
    429 
    430   // CPUName may have been set by the CPU detection code. Make sure the
    431   // new MCSchedModel is used.
    432   InitMCProcessorInfo(CPUName, FS);
    433 
    434   if (X86ProcFamily == IntelAtom)
    435     PostRAScheduler = true;
    436 
    437   InstrItins = getInstrItineraryForCPU(CPUName);
    438 
    439   // It's important to keep the MCSubtargetInfo feature bits in sync with
    440   // target data structure which is shared with MC code emitter, etc.
    441   if (In64BitMode)
    442     ToggleFeature(X86::Mode64Bit);
    443 
    444   DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel
    445                << ", 3DNowLevel " << X863DNowLevel
    446                << ", 64bit " << HasX86_64 << "\n");
    447   assert((!In64BitMode || HasX86_64) &&
    448          "64-bit code requested on a subtarget that doesn't support it!");
    449 
    450   // Stack alignment is 16 bytes on Darwin, Linux and Solaris (both
    451   // 32 and 64 bit) and for all 64-bit targets.
    452   if (StackAlignOverride)
    453     stackAlignment = StackAlignOverride;
    454   else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() ||
    455            In64BitMode)
    456     stackAlignment = 16;
    457 }
    458 
    459 void X86Subtarget::initializeEnvironment() {
    460   X86SSELevel = NoMMXSSE;
    461   X863DNowLevel = NoThreeDNow;
    462   HasCMov = false;
    463   HasX86_64 = false;
    464   HasPOPCNT = false;
    465   HasSSE4A = false;
    466   HasAES = false;
    467   HasPCLMUL = false;
    468   HasFMA = false;
    469   HasFMA4 = false;
    470   HasXOP = false;
    471   HasMOVBE = false;
    472   HasRDRAND = false;
    473   HasF16C = false;
    474   HasFSGSBase = false;
    475   HasLZCNT = false;
    476   HasBMI = false;
    477   HasBMI2 = false;
    478   HasRTM = false;
    479   HasHLE = false;
    480   HasERI = false;
    481   HasCDI = false;
    482   HasPFI=false;
    483   HasADX = false;
    484   HasPRFCHW = false;
    485   HasRDSEED = false;
    486   IsBTMemSlow = false;
    487   IsUAMemFast = false;
    488   HasVectorUAMem = false;
    489   HasCmpxchg16b = false;
    490   UseLeaForSP = false;
    491   HasSlowDivide = false;
    492   PostRAScheduler = false;
    493   PadShortFunctions = false;
    494   CallRegIndirect = false;
    495   LEAUsesAG = false;
    496   stackAlignment = 4;
    497   // FIXME: this is a known good value for Yonah. How about others?
    498   MaxInlineSizeThreshold = 128;
    499 }
    500 
    501 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
    502                            const std::string &FS,
    503                            unsigned StackAlignOverride, bool is64Bit)
    504   : X86GenSubtargetInfo(TT, CPU, FS)
    505   , X86ProcFamily(Others)
    506   , PICStyle(PICStyles::None)
    507   , TargetTriple(TT)
    508   , StackAlignOverride(StackAlignOverride)
    509   , In64BitMode(is64Bit) {
    510   initializeEnvironment();
    511   resetSubtargetFeatures(CPU, FS);
    512 }
    513 
    514 bool X86Subtarget::enablePostRAScheduler(
    515            CodeGenOpt::Level OptLevel,
    516            TargetSubtargetInfo::AntiDepBreakMode& Mode,
    517            RegClassVector& CriticalPathRCs) const {
    518   Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
    519   CriticalPathRCs.clear();
    520   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
    521 }
    522