1 //===-- FastISel.h - Definition of the FastISel class ---*- C++ -*---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// 10 /// \file 11 /// This file defines the FastISel class. 12 /// 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_FASTISEL_H 16 #define LLVM_CODEGEN_FASTISEL_H 17 18 #include "llvm/ADT/DenseMap.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/ValueTypes.h" 21 22 namespace llvm { 23 24 class AllocaInst; 25 class Constant; 26 class ConstantFP; 27 class FunctionLoweringInfo; 28 class Instruction; 29 class LoadInst; 30 class MachineConstantPool; 31 class MachineFunction; 32 class MachineInstr; 33 class MachineFrameInfo; 34 class MachineRegisterInfo; 35 class DataLayout; 36 class TargetInstrInfo; 37 class TargetLibraryInfo; 38 class TargetLowering; 39 class TargetMachine; 40 class TargetRegisterClass; 41 class TargetRegisterInfo; 42 class User; 43 class Value; 44 45 /// This is a fast-path instruction selection class that generates poor code and 46 /// doesn't support illegal types or non-trivial lowering, but runs quickly. 47 class FastISel { 48 protected: 49 DenseMap<const Value *, unsigned> LocalValueMap; 50 FunctionLoweringInfo &FuncInfo; 51 MachineRegisterInfo &MRI; 52 MachineFrameInfo &MFI; 53 MachineConstantPool &MCP; 54 DebugLoc DL; 55 const TargetMachine &TM; 56 const DataLayout &TD; 57 const TargetInstrInfo &TII; 58 const TargetLowering &TLI; 59 const TargetRegisterInfo &TRI; 60 const TargetLibraryInfo *LibInfo; 61 62 /// The position of the last instruction for materializing constants for use 63 /// in the current block. It resets to EmitStartPt when it makes sense (for 64 /// example, it's usually profitable to avoid function calls between the 65 /// definition and the use) 66 MachineInstr *LastLocalValue; 67 68 /// The top most instruction in the current block that is allowed for emitting 69 /// local variables. LastLocalValue resets to EmitStartPt when it makes sense 70 /// (for example, on function calls) 71 MachineInstr *EmitStartPt; 72 73 public: 74 /// Return the position of the last instruction emitted for materializing 75 /// constants for use in the current block. 76 MachineInstr *getLastLocalValue() { return LastLocalValue; } 77 78 /// Update the position of the last instruction emitted for materializing 79 /// constants for use in the current block. 80 void setLastLocalValue(MachineInstr *I) { 81 EmitStartPt = I; 82 LastLocalValue = I; 83 } 84 85 /// Set the current block to which generated machine instructions will be 86 /// appended, and clear the local CSE map. 87 void startNewBlock(); 88 89 /// Return current debug location information. 90 DebugLoc getCurDebugLoc() const { return DL; } 91 92 /// Do "fast" instruction selection for function arguments and append machine 93 /// instructions to the current block. Return true if it is successful. 94 bool LowerArguments(); 95 96 /// Do "fast" instruction selection for the given LLVM IR instruction, and 97 /// append generated machine instructions to the current block. Return true if 98 /// selection was successful. 99 bool SelectInstruction(const Instruction *I); 100 101 /// Do "fast" instruction selection for the given LLVM IR operator 102 /// (Instruction or ConstantExpr), and append generated machine instructions 103 /// to the current block. Return true if selection was successful. 104 bool SelectOperator(const User *I, unsigned Opcode); 105 106 /// Create a virtual register and arrange for it to be assigned the value for 107 /// the given LLVM value. 108 unsigned getRegForValue(const Value *V); 109 110 /// Look up the value to see if its value is already cached in a register. It 111 /// may be defined by instructions across blocks or defined locally. 112 unsigned lookUpRegForValue(const Value *V); 113 114 /// This is a wrapper around getRegForValue that also takes care of truncating 115 /// or sign-extending the given getelementptr index value. 116 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V); 117 118 /// \brief We're checking to see if we can fold \p LI into \p FoldInst. Note 119 /// that we could have a sequence where multiple LLVM IR instructions are 120 /// folded into the same machineinstr. For example we could have: 121 /// 122 /// A: x = load i32 *P 123 /// B: y = icmp A, 42 124 /// C: br y, ... 125 /// 126 /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B" 127 /// (and any other folded instructions) because it is between A and C. 128 /// 129 /// If we succeed folding, return true. 130 bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst); 131 132 /// \brief The specified machine instr operand is a vreg, and that vreg is 133 /// being provided by the specified load instruction. If possible, try to 134 /// fold the load as an operand to the instruction, returning true if 135 /// possible. 136 /// 137 /// This method should be implemented by targets. 138 virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/, 139 const LoadInst * /*LI*/) { 140 return false; 141 } 142 143 /// Reset InsertPt to prepare for inserting instructions into the current 144 /// block. 145 void recomputeInsertPt(); 146 147 /// Remove all dead instructions between the I and E. 148 void removeDeadCode(MachineBasicBlock::iterator I, 149 MachineBasicBlock::iterator E); 150 151 struct SavePoint { 152 MachineBasicBlock::iterator InsertPt; 153 DebugLoc DL; 154 }; 155 156 /// Prepare InsertPt to begin inserting instructions into the local value area 157 /// and return the old insert position. 158 SavePoint enterLocalValueArea(); 159 160 /// Reset InsertPt to the given old insert position. 161 void leaveLocalValueArea(SavePoint Old); 162 163 virtual ~FastISel(); 164 165 protected: 166 explicit FastISel(FunctionLoweringInfo &funcInfo, 167 const TargetLibraryInfo *libInfo); 168 169 /// This method is called by target-independent code when the normal FastISel 170 /// process fails to select an instruction. This gives targets a chance to 171 /// emit code for anything that doesn't fit into FastISel's framework. It 172 /// returns true if it was successful. 173 virtual bool 174 TargetSelectInstruction(const Instruction *I) = 0; 175 176 /// This method is called by target-independent code to do target specific 177 /// argument lowering. It returns true if it was successful. 178 virtual bool FastLowerArguments(); 179 180 /// This method is called by target-independent code to request that an 181 /// instruction with the given type and opcode be emitted. 182 virtual unsigned FastEmit_(MVT VT, 183 MVT RetVT, 184 unsigned Opcode); 185 186 /// This method is called by target-independent code to request that an 187 /// instruction with the given type, opcode, and register operand be emitted. 188 virtual unsigned FastEmit_r(MVT VT, 189 MVT RetVT, 190 unsigned Opcode, 191 unsigned Op0, bool Op0IsKill); 192 193 /// This method is called by target-independent code to request that an 194 /// instruction with the given type, opcode, and register operands be emitted. 195 virtual unsigned FastEmit_rr(MVT VT, 196 MVT RetVT, 197 unsigned Opcode, 198 unsigned Op0, bool Op0IsKill, 199 unsigned Op1, bool Op1IsKill); 200 201 /// This method is called by target-independent code to request that an 202 /// instruction with the given type, opcode, and register and immediate 203 /// operands be emitted. 204 virtual unsigned FastEmit_ri(MVT VT, 205 MVT RetVT, 206 unsigned Opcode, 207 unsigned Op0, bool Op0IsKill, 208 uint64_t Imm); 209 210 /// This method is called by target-independent code to request that an 211 /// instruction with the given type, opcode, and register and floating-point 212 /// immediate operands be emitted. 213 virtual unsigned FastEmit_rf(MVT VT, 214 MVT RetVT, 215 unsigned Opcode, 216 unsigned Op0, bool Op0IsKill, 217 const ConstantFP *FPImm); 218 219 /// This method is called by target-independent code to request that an 220 /// instruction with the given type, opcode, and register and immediate 221 /// operands be emitted. 222 virtual unsigned FastEmit_rri(MVT VT, 223 MVT RetVT, 224 unsigned Opcode, 225 unsigned Op0, bool Op0IsKill, 226 unsigned Op1, bool Op1IsKill, 227 uint64_t Imm); 228 229 /// \brief This method is a wrapper of FastEmit_ri. 230 /// 231 /// It first tries to emit an instruction with an immediate operand using 232 /// FastEmit_ri. If that fails, it materializes the immediate into a register 233 /// and try FastEmit_rr instead. 234 unsigned FastEmit_ri_(MVT VT, 235 unsigned Opcode, 236 unsigned Op0, bool Op0IsKill, 237 uint64_t Imm, MVT ImmType); 238 239 /// This method is called by target-independent code to request that an 240 /// instruction with the given type, opcode, and immediate operand be emitted. 241 virtual unsigned FastEmit_i(MVT VT, 242 MVT RetVT, 243 unsigned Opcode, 244 uint64_t Imm); 245 246 /// This method is called by target-independent code to request that an 247 /// instruction with the given type, opcode, and floating-point immediate 248 /// operand be emitted. 249 virtual unsigned FastEmit_f(MVT VT, 250 MVT RetVT, 251 unsigned Opcode, 252 const ConstantFP *FPImm); 253 254 /// Emit a MachineInstr with no operands and a result register in the given 255 /// register class. 256 unsigned FastEmitInst_(unsigned MachineInstOpcode, 257 const TargetRegisterClass *RC); 258 259 /// Emit a MachineInstr with one register operand and a result register in the 260 /// given register class. 261 unsigned FastEmitInst_r(unsigned MachineInstOpcode, 262 const TargetRegisterClass *RC, 263 unsigned Op0, bool Op0IsKill); 264 265 /// Emit a MachineInstr with two register operands and a result register in 266 /// the given register class. 267 unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 268 const TargetRegisterClass *RC, 269 unsigned Op0, bool Op0IsKill, 270 unsigned Op1, bool Op1IsKill); 271 272 /// Emit a MachineInstr with three register operands and a result register in 273 /// the given register class. 274 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode, 275 const TargetRegisterClass *RC, 276 unsigned Op0, bool Op0IsKill, 277 unsigned Op1, bool Op1IsKill, 278 unsigned Op2, bool Op2IsKill); 279 280 /// Emit a MachineInstr with a register operand, an immediate, and a result 281 /// register in the given register class. 282 unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 283 const TargetRegisterClass *RC, 284 unsigned Op0, bool Op0IsKill, 285 uint64_t Imm); 286 287 /// Emit a MachineInstr with one register operand and two immediate operands. 288 unsigned FastEmitInst_rii(unsigned MachineInstOpcode, 289 const TargetRegisterClass *RC, 290 unsigned Op0, bool Op0IsKill, 291 uint64_t Imm1, uint64_t Imm2); 292 293 /// Emit a MachineInstr with two register operands and a result register in 294 /// the given register class. 295 unsigned FastEmitInst_rf(unsigned MachineInstOpcode, 296 const TargetRegisterClass *RC, 297 unsigned Op0, bool Op0IsKill, 298 const ConstantFP *FPImm); 299 300 /// Emit a MachineInstr with two register operands, an immediate, and a result 301 /// register in the given register class. 302 unsigned FastEmitInst_rri(unsigned MachineInstOpcode, 303 const TargetRegisterClass *RC, 304 unsigned Op0, bool Op0IsKill, 305 unsigned Op1, bool Op1IsKill, 306 uint64_t Imm); 307 308 /// Emit a MachineInstr with two register operands, two immediates operands, 309 /// and a result register in the given register class. 310 unsigned FastEmitInst_rrii(unsigned MachineInstOpcode, 311 const TargetRegisterClass *RC, 312 unsigned Op0, bool Op0IsKill, 313 unsigned Op1, bool Op1IsKill, 314 uint64_t Imm1, uint64_t Imm2); 315 316 /// Emit a MachineInstr with a single immediate operand, and a result register 317 /// in the given register class. 318 unsigned FastEmitInst_i(unsigned MachineInstrOpcode, 319 const TargetRegisterClass *RC, 320 uint64_t Imm); 321 322 /// Emit a MachineInstr with a two immediate operands. 323 unsigned FastEmitInst_ii(unsigned MachineInstrOpcode, 324 const TargetRegisterClass *RC, 325 uint64_t Imm1, uint64_t Imm2); 326 327 /// Emit a MachineInstr for an extract_subreg from a specified index of a 328 /// superregister to a specified type. 329 unsigned FastEmitInst_extractsubreg(MVT RetVT, 330 unsigned Op0, bool Op0IsKill, 331 uint32_t Idx); 332 333 /// Emit MachineInstrs to compute the value of Op with all but the least 334 /// significant bit set to zero. 335 unsigned FastEmitZExtFromI1(MVT VT, 336 unsigned Op0, bool Op0IsKill); 337 338 /// Emit an unconditional branch to the given block, unless it is the 339 /// immediate (fall-through) successor, and update the CFG. 340 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL); 341 342 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1); 343 344 unsigned createResultReg(const TargetRegisterClass *RC); 345 346 /// Emit a constant in a register using target-specific logic, such as 347 /// constant pool loads. 348 virtual unsigned TargetMaterializeConstant(const Constant* C) { 349 return 0; 350 } 351 352 /// Emit an alloca address in a register using target-specific logic. 353 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) { 354 return 0; 355 } 356 357 virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) { 358 return 0; 359 } 360 361 private: 362 bool SelectBinaryOp(const User *I, unsigned ISDOpcode); 363 364 bool SelectFNeg(const User *I); 365 366 bool SelectGetElementPtr(const User *I); 367 368 bool SelectCall(const User *I); 369 370 bool SelectBitCast(const User *I); 371 372 bool SelectCast(const User *I, unsigned Opcode); 373 374 bool SelectExtractValue(const User *I); 375 376 bool SelectInsertValue(const User *I); 377 378 /// \brief Handle PHI nodes in successor blocks. 379 /// 380 /// Emit code to ensure constants are copied into registers when needed. 381 /// Remember the virtual registers that need to be added to the Machine PHI 382 /// nodes as input. We cannot just directly add them, because expansion might 383 /// result in multiple MBB's for one BB. As such, the start of the BB might 384 /// correspond to a different MBB than the end. 385 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB); 386 387 /// Helper for getRegForVale. This function is called when the value isn't 388 /// already available in a register and must be materialized with new 389 /// instructions. 390 unsigned materializeRegForValue(const Value *V, MVT VT); 391 392 /// Clears LocalValueMap and moves the area for the new local variables to the 393 /// beginning of the block. It helps to avoid spilling cached variables across 394 /// heavy instructions like calls. 395 void flushLocalValueMap(); 396 397 /// Test whether the given value has exactly one use. 398 bool hasTrivialKill(const Value *V) const; 399 }; 400 401 } 402 403 #endif 404
