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      1 //===-- llvm/MC/MCSchedule.h - Scheduling -----------------------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the classes used to describe a subtarget's machine model
     11 // for scheduling and other instruction cost heuristics.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef LLVM_MC_MCSCHEDULE_H
     16 #define LLVM_MC_MCSCHEDULE_H
     17 
     18 #include "llvm/Support/DataTypes.h"
     19 #include <cassert>
     20 
     21 namespace llvm {
     22 
     23 struct InstrItinerary;
     24 
     25 /// Define a kind of processor resource that will be modeled by the scheduler.
     26 struct MCProcResourceDesc {
     27 #ifndef NDEBUG
     28   const char *Name;
     29 #endif
     30   unsigned NumUnits; // Number of resource of this kind
     31   unsigned SuperIdx; // Index of the resources kind that contains this kind.
     32 
     33   // Number of resources that may be buffered.
     34   //
     35   // Buffered resources (BufferSize > 0 || BufferSize == -1) may be consumed at
     36   // some indeterminate cycle after dispatch (e.g. for instructions that may
     37   // issue out-of-order). Unbuffered resources (BufferSize == 0) always consume
     38   // their resource some fixed number of cycles after dispatch (e.g. for
     39   // instruction interlocking that may stall the pipeline).
     40   int BufferSize;
     41 
     42   bool operator==(const MCProcResourceDesc &Other) const {
     43     return NumUnits == Other.NumUnits && SuperIdx == Other.SuperIdx
     44       && BufferSize == Other.BufferSize;
     45   }
     46 };
     47 
     48 /// Identify one of the processor resource kinds consumed by a particular
     49 /// scheduling class for the specified number of cycles.
     50 struct MCWriteProcResEntry {
     51   unsigned ProcResourceIdx;
     52   unsigned Cycles;
     53 
     54   bool operator==(const MCWriteProcResEntry &Other) const {
     55     return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
     56   }
     57 };
     58 
     59 /// Specify the latency in cpu cycles for a particular scheduling class and def
     60 /// index. -1 indicates an invalid latency. Heuristics would typically consider
     61 /// an instruction with invalid latency to have infinite latency.  Also identify
     62 /// the WriteResources of this def. When the operand expands to a sequence of
     63 /// writes, this ID is the last write in the sequence.
     64 struct MCWriteLatencyEntry {
     65   int Cycles;
     66   unsigned WriteResourceID;
     67 
     68   bool operator==(const MCWriteLatencyEntry &Other) const {
     69     return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
     70   }
     71 };
     72 
     73 /// Specify the number of cycles allowed after instruction issue before a
     74 /// particular use operand reads its registers. This effectively reduces the
     75 /// write's latency. Here we allow negative cycles for corner cases where
     76 /// latency increases. This rule only applies when the entry's WriteResource
     77 /// matches the write's WriteResource.
     78 ///
     79 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by
     80 /// WriteResourceIdx.
     81 struct MCReadAdvanceEntry {
     82   unsigned UseIdx;
     83   unsigned WriteResourceID;
     84   int Cycles;
     85 
     86   bool operator==(const MCReadAdvanceEntry &Other) const {
     87     return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
     88       && Cycles == Other.Cycles;
     89   }
     90 };
     91 
     92 /// Summarize the scheduling resources required for an instruction of a
     93 /// particular scheduling class.
     94 ///
     95 /// Defined as an aggregate struct for creating tables with initializer lists.
     96 struct MCSchedClassDesc {
     97   static const unsigned short InvalidNumMicroOps = UINT16_MAX;
     98   static const unsigned short VariantNumMicroOps = UINT16_MAX - 1;
     99 
    100 #ifndef NDEBUG
    101   const char* Name;
    102 #endif
    103   unsigned short NumMicroOps;
    104   bool     BeginGroup;
    105   bool     EndGroup;
    106   unsigned WriteProcResIdx; // First index into WriteProcResTable.
    107   unsigned NumWriteProcResEntries;
    108   unsigned WriteLatencyIdx; // First index into WriteLatencyTable.
    109   unsigned NumWriteLatencyEntries;
    110   unsigned ReadAdvanceIdx; // First index into ReadAdvanceTable.
    111   unsigned NumReadAdvanceEntries;
    112 
    113   bool isValid() const {
    114     return NumMicroOps != InvalidNumMicroOps;
    115   }
    116   bool isVariant() const {
    117     return NumMicroOps == VariantNumMicroOps;
    118   }
    119 };
    120 
    121 /// Machine model for scheduling, bundling, and heuristics.
    122 ///
    123 /// The machine model directly provides basic information about the
    124 /// microarchitecture to the scheduler in the form of properties. It also
    125 /// optionally refers to scheduler resource tables and itinerary
    126 /// tables. Scheduler resource tables model the latency and cost for each
    127 /// instruction type. Itinerary tables are an independant mechanism that
    128 /// provides a detailed reservation table describing each cycle of instruction
    129 /// execution. Subtargets may define any or all of the above categories of data
    130 /// depending on the type of CPU and selected scheduler.
    131 class MCSchedModel {
    132 public:
    133   static MCSchedModel DefaultSchedModel; // For unknown processors.
    134 
    135   // IssueWidth is the maximum number of instructions that may be scheduled in
    136   // the same per-cycle group.
    137   unsigned IssueWidth;
    138   static const unsigned DefaultIssueWidth = 1;
    139 
    140   // MicroOpBufferSize is the number of micro-ops that the processor may buffer
    141   // for out-of-order execution.
    142   //
    143   // "0" means operations that are not ready in this cycle are not considered
    144   // for scheduling (they go in the pending queue). Latency is paramount. This
    145   // may be more efficient if many instructions are pending in a schedule.
    146   //
    147   // "1" means all instructions are considered for scheduling regardless of
    148   // whether they are ready in this cycle. Latency still causes issue stalls,
    149   // but we balance those stalls against other heuristics.
    150   //
    151   // "> 1" means the processor is out-of-order. This is a machine independent
    152   // estimate of highly machine specific characteristics such are the register
    153   // renaming pool and reorder buffer.
    154   unsigned MicroOpBufferSize;
    155   static const unsigned DefaultMicroOpBufferSize = 0;
    156 
    157   // LoadLatency is the expected latency of load instructions.
    158   //
    159   // If MinLatency >= 0, this may be overriden for individual load opcodes by
    160   // InstrItinerary OperandCycles.
    161   unsigned LoadLatency;
    162   static const unsigned DefaultLoadLatency = 4;
    163 
    164   // HighLatency is the expected latency of "very high latency" operations.
    165   // See TargetInstrInfo::isHighLatencyDef().
    166   // By default, this is set to an arbitrarily high number of cycles
    167   // likely to have some impact on scheduling heuristics.
    168   // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
    169   unsigned HighLatency;
    170   static const unsigned DefaultHighLatency = 10;
    171 
    172   // MispredictPenalty is the typical number of extra cycles the processor
    173   // takes to recover from a branch misprediction.
    174   unsigned MispredictPenalty;
    175   static const unsigned DefaultMispredictPenalty = 10;
    176 
    177 private:
    178   unsigned ProcID;
    179   const MCProcResourceDesc *ProcResourceTable;
    180   const MCSchedClassDesc *SchedClassTable;
    181   unsigned NumProcResourceKinds;
    182   unsigned NumSchedClasses;
    183   // Instruction itinerary tables used by InstrItineraryData.
    184   friend class InstrItineraryData;
    185   const InstrItinerary *InstrItineraries;
    186 
    187 public:
    188   // Default's must be specified as static const literals so that tablegenerated
    189   // target code can use it in static initializers. The defaults need to be
    190   // initialized in this default ctor because some clients directly instantiate
    191   // MCSchedModel instead of using a generated itinerary.
    192   MCSchedModel(): IssueWidth(DefaultIssueWidth),
    193                   MicroOpBufferSize(DefaultMicroOpBufferSize),
    194                   LoadLatency(DefaultLoadLatency),
    195                   HighLatency(DefaultHighLatency),
    196                   MispredictPenalty(DefaultMispredictPenalty),
    197                   ProcID(0), ProcResourceTable(0), SchedClassTable(0),
    198                   NumProcResourceKinds(0), NumSchedClasses(0),
    199                   InstrItineraries(0) {
    200     (void)NumProcResourceKinds;
    201     (void)NumSchedClasses;
    202   }
    203 
    204   // Table-gen driven ctor.
    205   MCSchedModel(unsigned iw, int mbs, unsigned ll, unsigned hl,
    206                unsigned mp, unsigned pi, const MCProcResourceDesc *pr,
    207                const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,
    208                const InstrItinerary *ii):
    209     IssueWidth(iw), MicroOpBufferSize(mbs), LoadLatency(ll), HighLatency(hl),
    210     MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr),
    211     SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc),
    212     InstrItineraries(ii) {}
    213 
    214   unsigned getProcessorID() const { return ProcID; }
    215 
    216   /// Does this machine model include instruction-level scheduling.
    217   bool hasInstrSchedModel() const { return SchedClassTable; }
    218 
    219   unsigned getNumProcResourceKinds() const {
    220     return NumProcResourceKinds;
    221   }
    222 
    223   const MCProcResourceDesc *getProcResource(unsigned ProcResourceIdx) const {
    224     assert(hasInstrSchedModel() && "No scheduling machine model");
    225 
    226     assert(ProcResourceIdx < NumProcResourceKinds && "bad proc resource idx");
    227     return &ProcResourceTable[ProcResourceIdx];
    228   }
    229 
    230   const MCSchedClassDesc *getSchedClassDesc(unsigned SchedClassIdx) const {
    231     assert(hasInstrSchedModel() && "No scheduling machine model");
    232 
    233     assert(SchedClassIdx < NumSchedClasses && "bad scheduling class idx");
    234     return &SchedClassTable[SchedClassIdx];
    235   }
    236 };
    237 
    238 } // End llvm namespace
    239 
    240 #endif
    241