1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H 16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H 17 18 #include "SystemZ.h" 19 #include "llvm/CodeGen/MachineBasicBlock.h" 20 #include "llvm/CodeGen/SelectionDAG.h" 21 #include "llvm/Target/TargetLowering.h" 22 23 namespace llvm { 24 namespace SystemZISD { 25 enum { 26 FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 28 // Return with a flag operand. Operand 0 is the chain operand. 29 RET_FLAG, 30 31 // Calls a function. Operand 0 is the chain operand and operand 1 32 // is the target address. The arguments start at operand 2. 33 // There is an optional glue operand at the end. 34 CALL, 35 36 // Wraps a TargetGlobalAddress that should be loaded using PC-relative 37 // accesses (LARL). Operand 0 is the address. 38 PCREL_WRAPPER, 39 40 // Signed integer and floating-point comparisons. The operands are the 41 // two values to compare. 42 CMP, 43 44 // Likewise unsigned integer comparison. 45 UCMP, 46 47 // Branches if a condition is true. Operand 0 is the chain operand; 48 // operand 1 is the 4-bit condition-code mask, with bit N in 49 // big-endian order meaning "branch if CC=N"; operand 2 is the 50 // target block and operand 3 is the flag operand. 51 BR_CCMASK, 52 53 // Selects between operand 0 and operand 1. Operand 2 is the 54 // mask of condition-code values for which operand 0 should be 55 // chosen over operand 1; it has the same form as BR_CCMASK. 56 // Operand 3 is the flag operand. 57 SELECT_CCMASK, 58 59 // Evaluates to the gap between the stack pointer and the 60 // base of the dynamically-allocatable area. 61 ADJDYNALLOC, 62 63 // Extracts the value of a 32-bit access register. Operand 0 is 64 // the number of the register. 65 EXTRACT_ACCESS, 66 67 // Wrappers around the ISD opcodes of the same name. The output and 68 // first input operands are GR128s. The trailing numbers are the 69 // widths of the second operand in bits. 70 UMUL_LOHI64, 71 SDIVREM32, 72 SDIVREM64, 73 UDIVREM32, 74 UDIVREM64, 75 76 // Use MVC to copy bytes from one memory location to another. 77 // The first operand is the target address, the second operand is the 78 // source address, and the third operand is the constant length. 79 // This isn't a memory opcode because we'd need to attach two 80 // MachineMemOperands rather than one. 81 MVC, 82 83 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or 84 // ATOMIC_LOAD_<op>. 85 // 86 // Operand 0: the address of the containing 32-bit-aligned field 87 // Operand 1: the second operand of <op>, in the high bits of an i32 88 // for everything except ATOMIC_SWAPW 89 // Operand 2: how many bits to rotate the i32 left to bring the first 90 // operand into the high bits 91 // Operand 3: the negative of operand 2, for rotating the other way 92 // Operand 4: the width of the field in bits (8 or 16) 93 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE, 94 ATOMIC_LOADW_ADD, 95 ATOMIC_LOADW_SUB, 96 ATOMIC_LOADW_AND, 97 ATOMIC_LOADW_OR, 98 ATOMIC_LOADW_XOR, 99 ATOMIC_LOADW_NAND, 100 ATOMIC_LOADW_MIN, 101 ATOMIC_LOADW_MAX, 102 ATOMIC_LOADW_UMIN, 103 ATOMIC_LOADW_UMAX, 104 105 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP. 106 // 107 // Operand 0: the address of the containing 32-bit-aligned field 108 // Operand 1: the compare value, in the low bits of an i32 109 // Operand 2: the swap value, in the low bits of an i32 110 // Operand 3: how many bits to rotate the i32 left to bring the first 111 // operand into the high bits 112 // Operand 4: the negative of operand 2, for rotating the other way 113 // Operand 5: the width of the field in bits (8 or 16) 114 ATOMIC_CMP_SWAPW 115 }; 116 } 117 118 class SystemZSubtarget; 119 class SystemZTargetMachine; 120 121 class SystemZTargetLowering : public TargetLowering { 122 public: 123 explicit SystemZTargetLowering(SystemZTargetMachine &TM); 124 125 // Override TargetLowering. 126 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE { 127 return MVT::i32; 128 } 129 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE { 130 return MVT::i32; 131 } 132 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE; 133 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE; 134 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const 135 LLVM_OVERRIDE; 136 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const 137 LLVM_OVERRIDE; 138 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE; 139 virtual std::pair<unsigned, const TargetRegisterClass *> 140 getRegForInlineAsmConstraint(const std::string &Constraint, 141 MVT VT) const LLVM_OVERRIDE; 142 virtual TargetLowering::ConstraintType 143 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE; 144 virtual TargetLowering::ConstraintWeight 145 getSingleConstraintMatchWeight(AsmOperandInfo &info, 146 const char *constraint) const LLVM_OVERRIDE; 147 virtual void 148 LowerAsmOperandForConstraint(SDValue Op, 149 std::string &Constraint, 150 std::vector<SDValue> &Ops, 151 SelectionDAG &DAG) const LLVM_OVERRIDE; 152 virtual MachineBasicBlock * 153 EmitInstrWithCustomInserter(MachineInstr *MI, 154 MachineBasicBlock *BB) const LLVM_OVERRIDE; 155 virtual SDValue LowerOperation(SDValue Op, 156 SelectionDAG &DAG) const LLVM_OVERRIDE; 157 virtual SDValue 158 LowerFormalArguments(SDValue Chain, 159 CallingConv::ID CallConv, bool isVarArg, 160 const SmallVectorImpl<ISD::InputArg> &Ins, 161 SDLoc DL, SelectionDAG &DAG, 162 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE; 163 virtual SDValue 164 LowerCall(CallLoweringInfo &CLI, 165 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE; 166 167 virtual SDValue 168 LowerReturn(SDValue Chain, 169 CallingConv::ID CallConv, bool IsVarArg, 170 const SmallVectorImpl<ISD::OutputArg> &Outs, 171 const SmallVectorImpl<SDValue> &OutVals, 172 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE; 173 174 private: 175 const SystemZSubtarget &Subtarget; 176 const SystemZTargetMachine &TM; 177 178 // Implement LowerOperation for individual opcodes. 179 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 180 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 181 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node, 182 SelectionDAG &DAG) const; 183 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node, 184 SelectionDAG &DAG) const; 185 SDValue lowerBlockAddress(BlockAddressSDNode *Node, 186 SelectionDAG &DAG) const; 187 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const; 188 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; 189 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 190 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const; 191 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 192 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const; 193 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const; 194 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const; 195 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const; 196 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const; 197 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG, 198 unsigned Opcode) const; 199 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const; 200 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const; 201 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const; 202 203 // If the last instruction before MBBI in MBB was some form of COMPARE, 204 // try to replace it with a COMPARE AND BRANCH just before MBBI. 205 // CCMask and Target are the BRC-like operands for the branch. 206 // Return true if the change was made. 207 bool convertPrevCompareToBranch(MachineBasicBlock *MBB, 208 MachineBasicBlock::iterator MBBI, 209 unsigned CCMask, 210 MachineBasicBlock *Target) const; 211 212 // Implement EmitInstrWithCustomInserter for individual operation types. 213 MachineBasicBlock *emitSelect(MachineInstr *MI, 214 MachineBasicBlock *BB) const; 215 MachineBasicBlock *emitCondStore(MachineInstr *MI, 216 MachineBasicBlock *BB, 217 unsigned StoreOpcode, unsigned STOCOpcode, 218 bool Invert) const; 219 MachineBasicBlock *emitExt128(MachineInstr *MI, 220 MachineBasicBlock *MBB, 221 bool ClearEven, unsigned SubReg) const; 222 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI, 223 MachineBasicBlock *BB, 224 unsigned BinOpcode, unsigned BitSize, 225 bool Invert = false) const; 226 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI, 227 MachineBasicBlock *MBB, 228 unsigned CompareOpcode, 229 unsigned KeepOldMask, 230 unsigned BitSize) const; 231 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI, 232 MachineBasicBlock *BB) const; 233 MachineBasicBlock *emitMVCWrapper(MachineInstr *MI, 234 MachineBasicBlock *BB) const; 235 }; 236 } // end namespace llvm 237 238 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H 239
