1 //===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the TargetLoweringBase class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetLowering.h" 15 #include "llvm/ADT/BitVector.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/Triple.h" 18 #include "llvm/CodeGen/Analysis.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineJumpTableInfo.h" 22 #include "llvm/IR/DataLayout.h" 23 #include "llvm/IR/DerivedTypes.h" 24 #include "llvm/IR/GlobalVariable.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/Support/CommandLine.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/MathExtras.h" 30 #include "llvm/Target/TargetLoweringObjectFile.h" 31 #include "llvm/Target/TargetMachine.h" 32 #include "llvm/Target/TargetRegisterInfo.h" 33 #include <cctype> 34 using namespace llvm; 35 36 /// InitLibcallNames - Set default libcall names. 37 /// 38 static void InitLibcallNames(const char **Names, const TargetMachine &TM) { 39 Names[RTLIB::SHL_I16] = "__ashlhi3"; 40 Names[RTLIB::SHL_I32] = "__ashlsi3"; 41 Names[RTLIB::SHL_I64] = "__ashldi3"; 42 Names[RTLIB::SHL_I128] = "__ashlti3"; 43 Names[RTLIB::SRL_I16] = "__lshrhi3"; 44 Names[RTLIB::SRL_I32] = "__lshrsi3"; 45 Names[RTLIB::SRL_I64] = "__lshrdi3"; 46 Names[RTLIB::SRL_I128] = "__lshrti3"; 47 Names[RTLIB::SRA_I16] = "__ashrhi3"; 48 Names[RTLIB::SRA_I32] = "__ashrsi3"; 49 Names[RTLIB::SRA_I64] = "__ashrdi3"; 50 Names[RTLIB::SRA_I128] = "__ashrti3"; 51 Names[RTLIB::MUL_I8] = "__mulqi3"; 52 Names[RTLIB::MUL_I16] = "__mulhi3"; 53 Names[RTLIB::MUL_I32] = "__mulsi3"; 54 Names[RTLIB::MUL_I64] = "__muldi3"; 55 Names[RTLIB::MUL_I128] = "__multi3"; 56 Names[RTLIB::MULO_I32] = "__mulosi4"; 57 Names[RTLIB::MULO_I64] = "__mulodi4"; 58 Names[RTLIB::MULO_I128] = "__muloti4"; 59 Names[RTLIB::SDIV_I8] = "__divqi3"; 60 Names[RTLIB::SDIV_I16] = "__divhi3"; 61 Names[RTLIB::SDIV_I32] = "__divsi3"; 62 Names[RTLIB::SDIV_I64] = "__divdi3"; 63 Names[RTLIB::SDIV_I128] = "__divti3"; 64 Names[RTLIB::UDIV_I8] = "__udivqi3"; 65 Names[RTLIB::UDIV_I16] = "__udivhi3"; 66 Names[RTLIB::UDIV_I32] = "__udivsi3"; 67 Names[RTLIB::UDIV_I64] = "__udivdi3"; 68 Names[RTLIB::UDIV_I128] = "__udivti3"; 69 Names[RTLIB::SREM_I8] = "__modqi3"; 70 Names[RTLIB::SREM_I16] = "__modhi3"; 71 Names[RTLIB::SREM_I32] = "__modsi3"; 72 Names[RTLIB::SREM_I64] = "__moddi3"; 73 Names[RTLIB::SREM_I128] = "__modti3"; 74 Names[RTLIB::UREM_I8] = "__umodqi3"; 75 Names[RTLIB::UREM_I16] = "__umodhi3"; 76 Names[RTLIB::UREM_I32] = "__umodsi3"; 77 Names[RTLIB::UREM_I64] = "__umoddi3"; 78 Names[RTLIB::UREM_I128] = "__umodti3"; 79 80 // These are generally not available. 81 Names[RTLIB::SDIVREM_I8] = 0; 82 Names[RTLIB::SDIVREM_I16] = 0; 83 Names[RTLIB::SDIVREM_I32] = 0; 84 Names[RTLIB::SDIVREM_I64] = 0; 85 Names[RTLIB::SDIVREM_I128] = 0; 86 Names[RTLIB::UDIVREM_I8] = 0; 87 Names[RTLIB::UDIVREM_I16] = 0; 88 Names[RTLIB::UDIVREM_I32] = 0; 89 Names[RTLIB::UDIVREM_I64] = 0; 90 Names[RTLIB::UDIVREM_I128] = 0; 91 92 Names[RTLIB::NEG_I32] = "__negsi2"; 93 Names[RTLIB::NEG_I64] = "__negdi2"; 94 Names[RTLIB::ADD_F32] = "__addsf3"; 95 Names[RTLIB::ADD_F64] = "__adddf3"; 96 Names[RTLIB::ADD_F80] = "__addxf3"; 97 Names[RTLIB::ADD_F128] = "__addtf3"; 98 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd"; 99 Names[RTLIB::SUB_F32] = "__subsf3"; 100 Names[RTLIB::SUB_F64] = "__subdf3"; 101 Names[RTLIB::SUB_F80] = "__subxf3"; 102 Names[RTLIB::SUB_F128] = "__subtf3"; 103 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub"; 104 Names[RTLIB::MUL_F32] = "__mulsf3"; 105 Names[RTLIB::MUL_F64] = "__muldf3"; 106 Names[RTLIB::MUL_F80] = "__mulxf3"; 107 Names[RTLIB::MUL_F128] = "__multf3"; 108 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul"; 109 Names[RTLIB::DIV_F32] = "__divsf3"; 110 Names[RTLIB::DIV_F64] = "__divdf3"; 111 Names[RTLIB::DIV_F80] = "__divxf3"; 112 Names[RTLIB::DIV_F128] = "__divtf3"; 113 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv"; 114 Names[RTLIB::REM_F32] = "fmodf"; 115 Names[RTLIB::REM_F64] = "fmod"; 116 Names[RTLIB::REM_F80] = "fmodl"; 117 Names[RTLIB::REM_F128] = "fmodl"; 118 Names[RTLIB::REM_PPCF128] = "fmodl"; 119 Names[RTLIB::FMA_F32] = "fmaf"; 120 Names[RTLIB::FMA_F64] = "fma"; 121 Names[RTLIB::FMA_F80] = "fmal"; 122 Names[RTLIB::FMA_F128] = "fmal"; 123 Names[RTLIB::FMA_PPCF128] = "fmal"; 124 Names[RTLIB::POWI_F32] = "__powisf2"; 125 Names[RTLIB::POWI_F64] = "__powidf2"; 126 Names[RTLIB::POWI_F80] = "__powixf2"; 127 Names[RTLIB::POWI_F128] = "__powitf2"; 128 Names[RTLIB::POWI_PPCF128] = "__powitf2"; 129 Names[RTLIB::SQRT_F32] = "sqrtf"; 130 Names[RTLIB::SQRT_F64] = "sqrt"; 131 Names[RTLIB::SQRT_F80] = "sqrtl"; 132 Names[RTLIB::SQRT_F128] = "sqrtl"; 133 Names[RTLIB::SQRT_PPCF128] = "sqrtl"; 134 Names[RTLIB::LOG_F32] = "logf"; 135 Names[RTLIB::LOG_F64] = "log"; 136 Names[RTLIB::LOG_F80] = "logl"; 137 Names[RTLIB::LOG_F128] = "logl"; 138 Names[RTLIB::LOG_PPCF128] = "logl"; 139 Names[RTLIB::LOG2_F32] = "log2f"; 140 Names[RTLIB::LOG2_F64] = "log2"; 141 Names[RTLIB::LOG2_F80] = "log2l"; 142 Names[RTLIB::LOG2_F128] = "log2l"; 143 Names[RTLIB::LOG2_PPCF128] = "log2l"; 144 Names[RTLIB::LOG10_F32] = "log10f"; 145 Names[RTLIB::LOG10_F64] = "log10"; 146 Names[RTLIB::LOG10_F80] = "log10l"; 147 Names[RTLIB::LOG10_F128] = "log10l"; 148 Names[RTLIB::LOG10_PPCF128] = "log10l"; 149 Names[RTLIB::EXP_F32] = "expf"; 150 Names[RTLIB::EXP_F64] = "exp"; 151 Names[RTLIB::EXP_F80] = "expl"; 152 Names[RTLIB::EXP_F128] = "expl"; 153 Names[RTLIB::EXP_PPCF128] = "expl"; 154 Names[RTLIB::EXP2_F32] = "exp2f"; 155 Names[RTLIB::EXP2_F64] = "exp2"; 156 Names[RTLIB::EXP2_F80] = "exp2l"; 157 Names[RTLIB::EXP2_F128] = "exp2l"; 158 Names[RTLIB::EXP2_PPCF128] = "exp2l"; 159 Names[RTLIB::SIN_F32] = "sinf"; 160 Names[RTLIB::SIN_F64] = "sin"; 161 Names[RTLIB::SIN_F80] = "sinl"; 162 Names[RTLIB::SIN_F128] = "sinl"; 163 Names[RTLIB::SIN_PPCF128] = "sinl"; 164 Names[RTLIB::COS_F32] = "cosf"; 165 Names[RTLIB::COS_F64] = "cos"; 166 Names[RTLIB::COS_F80] = "cosl"; 167 Names[RTLIB::COS_F128] = "cosl"; 168 Names[RTLIB::COS_PPCF128] = "cosl"; 169 Names[RTLIB::POW_F32] = "powf"; 170 Names[RTLIB::POW_F64] = "pow"; 171 Names[RTLIB::POW_F80] = "powl"; 172 Names[RTLIB::POW_F128] = "powl"; 173 Names[RTLIB::POW_PPCF128] = "powl"; 174 Names[RTLIB::CEIL_F32] = "ceilf"; 175 Names[RTLIB::CEIL_F64] = "ceil"; 176 Names[RTLIB::CEIL_F80] = "ceill"; 177 Names[RTLIB::CEIL_F128] = "ceill"; 178 Names[RTLIB::CEIL_PPCF128] = "ceill"; 179 Names[RTLIB::TRUNC_F32] = "truncf"; 180 Names[RTLIB::TRUNC_F64] = "trunc"; 181 Names[RTLIB::TRUNC_F80] = "truncl"; 182 Names[RTLIB::TRUNC_F128] = "truncl"; 183 Names[RTLIB::TRUNC_PPCF128] = "truncl"; 184 Names[RTLIB::RINT_F32] = "rintf"; 185 Names[RTLIB::RINT_F64] = "rint"; 186 Names[RTLIB::RINT_F80] = "rintl"; 187 Names[RTLIB::RINT_F128] = "rintl"; 188 Names[RTLIB::RINT_PPCF128] = "rintl"; 189 Names[RTLIB::NEARBYINT_F32] = "nearbyintf"; 190 Names[RTLIB::NEARBYINT_F64] = "nearbyint"; 191 Names[RTLIB::NEARBYINT_F80] = "nearbyintl"; 192 Names[RTLIB::NEARBYINT_F128] = "nearbyintl"; 193 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl"; 194 Names[RTLIB::FLOOR_F32] = "floorf"; 195 Names[RTLIB::FLOOR_F64] = "floor"; 196 Names[RTLIB::FLOOR_F80] = "floorl"; 197 Names[RTLIB::FLOOR_F128] = "floorl"; 198 Names[RTLIB::FLOOR_PPCF128] = "floorl"; 199 Names[RTLIB::COPYSIGN_F32] = "copysignf"; 200 Names[RTLIB::COPYSIGN_F64] = "copysign"; 201 Names[RTLIB::COPYSIGN_F80] = "copysignl"; 202 Names[RTLIB::COPYSIGN_F128] = "copysignl"; 203 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl"; 204 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2"; 205 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2"; 206 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2"; 207 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee"; 208 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee"; 209 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2"; 210 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2"; 211 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2"; 212 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2"; 213 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2"; 214 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2"; 215 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2"; 216 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi"; 217 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi"; 218 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi"; 219 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi"; 220 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti"; 221 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi"; 222 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi"; 223 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi"; 224 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi"; 225 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti"; 226 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi"; 227 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi"; 228 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti"; 229 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi"; 230 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi"; 231 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti"; 232 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi"; 233 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi"; 234 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti"; 235 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi"; 236 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi"; 237 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi"; 238 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi"; 239 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti"; 240 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi"; 241 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi"; 242 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi"; 243 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi"; 244 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti"; 245 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi"; 246 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi"; 247 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti"; 248 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi"; 249 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi"; 250 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti"; 251 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi"; 252 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi"; 253 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti"; 254 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf"; 255 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf"; 256 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf"; 257 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf"; 258 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf"; 259 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf"; 260 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf"; 261 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf"; 262 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf"; 263 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf"; 264 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf"; 265 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf"; 266 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf"; 267 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf"; 268 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf"; 269 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf"; 270 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf"; 271 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf"; 272 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf"; 273 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf"; 274 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf"; 275 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf"; 276 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf"; 277 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf"; 278 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf"; 279 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf"; 280 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf"; 281 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf"; 282 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf"; 283 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf"; 284 Names[RTLIB::OEQ_F32] = "__eqsf2"; 285 Names[RTLIB::OEQ_F64] = "__eqdf2"; 286 Names[RTLIB::OEQ_F128] = "__eqtf2"; 287 Names[RTLIB::UNE_F32] = "__nesf2"; 288 Names[RTLIB::UNE_F64] = "__nedf2"; 289 Names[RTLIB::UNE_F128] = "__netf2"; 290 Names[RTLIB::OGE_F32] = "__gesf2"; 291 Names[RTLIB::OGE_F64] = "__gedf2"; 292 Names[RTLIB::OGE_F128] = "__getf2"; 293 Names[RTLIB::OLT_F32] = "__ltsf2"; 294 Names[RTLIB::OLT_F64] = "__ltdf2"; 295 Names[RTLIB::OLT_F128] = "__lttf2"; 296 Names[RTLIB::OLE_F32] = "__lesf2"; 297 Names[RTLIB::OLE_F64] = "__ledf2"; 298 Names[RTLIB::OLE_F128] = "__letf2"; 299 Names[RTLIB::OGT_F32] = "__gtsf2"; 300 Names[RTLIB::OGT_F64] = "__gtdf2"; 301 Names[RTLIB::OGT_F128] = "__gttf2"; 302 Names[RTLIB::UO_F32] = "__unordsf2"; 303 Names[RTLIB::UO_F64] = "__unorddf2"; 304 Names[RTLIB::UO_F128] = "__unordtf2"; 305 Names[RTLIB::O_F32] = "__unordsf2"; 306 Names[RTLIB::O_F64] = "__unorddf2"; 307 Names[RTLIB::O_F128] = "__unordtf2"; 308 Names[RTLIB::MEMCPY] = "memcpy"; 309 Names[RTLIB::MEMMOVE] = "memmove"; 310 Names[RTLIB::MEMSET] = "memset"; 311 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume"; 312 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1"; 313 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2"; 314 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4"; 315 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8"; 316 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1"; 317 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2"; 318 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4"; 319 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8"; 320 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1"; 321 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2"; 322 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4"; 323 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8"; 324 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1"; 325 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2"; 326 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4"; 327 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8"; 328 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1"; 329 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2"; 330 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4"; 331 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8"; 332 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1"; 333 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2"; 334 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4"; 335 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8"; 336 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1"; 337 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2"; 338 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4"; 339 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8"; 340 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1"; 341 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2"; 342 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4"; 343 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8"; 344 345 if (Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU) { 346 Names[RTLIB::SINCOS_F32] = "sincosf"; 347 Names[RTLIB::SINCOS_F64] = "sincos"; 348 Names[RTLIB::SINCOS_F80] = "sincosl"; 349 Names[RTLIB::SINCOS_F128] = "sincosl"; 350 Names[RTLIB::SINCOS_PPCF128] = "sincosl"; 351 } else { 352 // These are generally not available. 353 Names[RTLIB::SINCOS_F32] = 0; 354 Names[RTLIB::SINCOS_F64] = 0; 355 Names[RTLIB::SINCOS_F80] = 0; 356 Names[RTLIB::SINCOS_F128] = 0; 357 Names[RTLIB::SINCOS_PPCF128] = 0; 358 } 359 } 360 361 /// InitLibcallCallingConvs - Set default libcall CallingConvs. 362 /// 363 static void InitLibcallCallingConvs(CallingConv::ID *CCs) { 364 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) { 365 CCs[i] = CallingConv::C; 366 } 367 } 368 369 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 370 /// UNKNOWN_LIBCALL if there is none. 371 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 372 if (OpVT == MVT::f32) { 373 if (RetVT == MVT::f64) 374 return FPEXT_F32_F64; 375 if (RetVT == MVT::f128) 376 return FPEXT_F32_F128; 377 } else if (OpVT == MVT::f64) { 378 if (RetVT == MVT::f128) 379 return FPEXT_F64_F128; 380 } 381 382 return UNKNOWN_LIBCALL; 383 } 384 385 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 386 /// UNKNOWN_LIBCALL if there is none. 387 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 388 if (RetVT == MVT::f32) { 389 if (OpVT == MVT::f64) 390 return FPROUND_F64_F32; 391 if (OpVT == MVT::f80) 392 return FPROUND_F80_F32; 393 if (OpVT == MVT::f128) 394 return FPROUND_F128_F32; 395 if (OpVT == MVT::ppcf128) 396 return FPROUND_PPCF128_F32; 397 } else if (RetVT == MVT::f64) { 398 if (OpVT == MVT::f80) 399 return FPROUND_F80_F64; 400 if (OpVT == MVT::f128) 401 return FPROUND_F128_F64; 402 if (OpVT == MVT::ppcf128) 403 return FPROUND_PPCF128_F64; 404 } 405 406 return UNKNOWN_LIBCALL; 407 } 408 409 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 410 /// UNKNOWN_LIBCALL if there is none. 411 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 412 if (OpVT == MVT::f32) { 413 if (RetVT == MVT::i8) 414 return FPTOSINT_F32_I8; 415 if (RetVT == MVT::i16) 416 return FPTOSINT_F32_I16; 417 if (RetVT == MVT::i32) 418 return FPTOSINT_F32_I32; 419 if (RetVT == MVT::i64) 420 return FPTOSINT_F32_I64; 421 if (RetVT == MVT::i128) 422 return FPTOSINT_F32_I128; 423 } else if (OpVT == MVT::f64) { 424 if (RetVT == MVT::i8) 425 return FPTOSINT_F64_I8; 426 if (RetVT == MVT::i16) 427 return FPTOSINT_F64_I16; 428 if (RetVT == MVT::i32) 429 return FPTOSINT_F64_I32; 430 if (RetVT == MVT::i64) 431 return FPTOSINT_F64_I64; 432 if (RetVT == MVT::i128) 433 return FPTOSINT_F64_I128; 434 } else if (OpVT == MVT::f80) { 435 if (RetVT == MVT::i32) 436 return FPTOSINT_F80_I32; 437 if (RetVT == MVT::i64) 438 return FPTOSINT_F80_I64; 439 if (RetVT == MVT::i128) 440 return FPTOSINT_F80_I128; 441 } else if (OpVT == MVT::f128) { 442 if (RetVT == MVT::i32) 443 return FPTOSINT_F128_I32; 444 if (RetVT == MVT::i64) 445 return FPTOSINT_F128_I64; 446 if (RetVT == MVT::i128) 447 return FPTOSINT_F128_I128; 448 } else if (OpVT == MVT::ppcf128) { 449 if (RetVT == MVT::i32) 450 return FPTOSINT_PPCF128_I32; 451 if (RetVT == MVT::i64) 452 return FPTOSINT_PPCF128_I64; 453 if (RetVT == MVT::i128) 454 return FPTOSINT_PPCF128_I128; 455 } 456 return UNKNOWN_LIBCALL; 457 } 458 459 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 460 /// UNKNOWN_LIBCALL if there is none. 461 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 462 if (OpVT == MVT::f32) { 463 if (RetVT == MVT::i8) 464 return FPTOUINT_F32_I8; 465 if (RetVT == MVT::i16) 466 return FPTOUINT_F32_I16; 467 if (RetVT == MVT::i32) 468 return FPTOUINT_F32_I32; 469 if (RetVT == MVT::i64) 470 return FPTOUINT_F32_I64; 471 if (RetVT == MVT::i128) 472 return FPTOUINT_F32_I128; 473 } else if (OpVT == MVT::f64) { 474 if (RetVT == MVT::i8) 475 return FPTOUINT_F64_I8; 476 if (RetVT == MVT::i16) 477 return FPTOUINT_F64_I16; 478 if (RetVT == MVT::i32) 479 return FPTOUINT_F64_I32; 480 if (RetVT == MVT::i64) 481 return FPTOUINT_F64_I64; 482 if (RetVT == MVT::i128) 483 return FPTOUINT_F64_I128; 484 } else if (OpVT == MVT::f80) { 485 if (RetVT == MVT::i32) 486 return FPTOUINT_F80_I32; 487 if (RetVT == MVT::i64) 488 return FPTOUINT_F80_I64; 489 if (RetVT == MVT::i128) 490 return FPTOUINT_F80_I128; 491 } else if (OpVT == MVT::f128) { 492 if (RetVT == MVT::i32) 493 return FPTOUINT_F128_I32; 494 if (RetVT == MVT::i64) 495 return FPTOUINT_F128_I64; 496 if (RetVT == MVT::i128) 497 return FPTOUINT_F128_I128; 498 } else if (OpVT == MVT::ppcf128) { 499 if (RetVT == MVT::i32) 500 return FPTOUINT_PPCF128_I32; 501 if (RetVT == MVT::i64) 502 return FPTOUINT_PPCF128_I64; 503 if (RetVT == MVT::i128) 504 return FPTOUINT_PPCF128_I128; 505 } 506 return UNKNOWN_LIBCALL; 507 } 508 509 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 510 /// UNKNOWN_LIBCALL if there is none. 511 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 512 if (OpVT == MVT::i32) { 513 if (RetVT == MVT::f32) 514 return SINTTOFP_I32_F32; 515 if (RetVT == MVT::f64) 516 return SINTTOFP_I32_F64; 517 if (RetVT == MVT::f80) 518 return SINTTOFP_I32_F80; 519 if (RetVT == MVT::f128) 520 return SINTTOFP_I32_F128; 521 if (RetVT == MVT::ppcf128) 522 return SINTTOFP_I32_PPCF128; 523 } else if (OpVT == MVT::i64) { 524 if (RetVT == MVT::f32) 525 return SINTTOFP_I64_F32; 526 if (RetVT == MVT::f64) 527 return SINTTOFP_I64_F64; 528 if (RetVT == MVT::f80) 529 return SINTTOFP_I64_F80; 530 if (RetVT == MVT::f128) 531 return SINTTOFP_I64_F128; 532 if (RetVT == MVT::ppcf128) 533 return SINTTOFP_I64_PPCF128; 534 } else if (OpVT == MVT::i128) { 535 if (RetVT == MVT::f32) 536 return SINTTOFP_I128_F32; 537 if (RetVT == MVT::f64) 538 return SINTTOFP_I128_F64; 539 if (RetVT == MVT::f80) 540 return SINTTOFP_I128_F80; 541 if (RetVT == MVT::f128) 542 return SINTTOFP_I128_F128; 543 if (RetVT == MVT::ppcf128) 544 return SINTTOFP_I128_PPCF128; 545 } 546 return UNKNOWN_LIBCALL; 547 } 548 549 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 550 /// UNKNOWN_LIBCALL if there is none. 551 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 552 if (OpVT == MVT::i32) { 553 if (RetVT == MVT::f32) 554 return UINTTOFP_I32_F32; 555 if (RetVT == MVT::f64) 556 return UINTTOFP_I32_F64; 557 if (RetVT == MVT::f80) 558 return UINTTOFP_I32_F80; 559 if (RetVT == MVT::f128) 560 return UINTTOFP_I32_F128; 561 if (RetVT == MVT::ppcf128) 562 return UINTTOFP_I32_PPCF128; 563 } else if (OpVT == MVT::i64) { 564 if (RetVT == MVT::f32) 565 return UINTTOFP_I64_F32; 566 if (RetVT == MVT::f64) 567 return UINTTOFP_I64_F64; 568 if (RetVT == MVT::f80) 569 return UINTTOFP_I64_F80; 570 if (RetVT == MVT::f128) 571 return UINTTOFP_I64_F128; 572 if (RetVT == MVT::ppcf128) 573 return UINTTOFP_I64_PPCF128; 574 } else if (OpVT == MVT::i128) { 575 if (RetVT == MVT::f32) 576 return UINTTOFP_I128_F32; 577 if (RetVT == MVT::f64) 578 return UINTTOFP_I128_F64; 579 if (RetVT == MVT::f80) 580 return UINTTOFP_I128_F80; 581 if (RetVT == MVT::f128) 582 return UINTTOFP_I128_F128; 583 if (RetVT == MVT::ppcf128) 584 return UINTTOFP_I128_PPCF128; 585 } 586 return UNKNOWN_LIBCALL; 587 } 588 589 /// InitCmpLibcallCCs - Set default comparison libcall CC. 590 /// 591 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 592 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); 593 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 594 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 595 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 596 CCs[RTLIB::UNE_F32] = ISD::SETNE; 597 CCs[RTLIB::UNE_F64] = ISD::SETNE; 598 CCs[RTLIB::UNE_F128] = ISD::SETNE; 599 CCs[RTLIB::OGE_F32] = ISD::SETGE; 600 CCs[RTLIB::OGE_F64] = ISD::SETGE; 601 CCs[RTLIB::OGE_F128] = ISD::SETGE; 602 CCs[RTLIB::OLT_F32] = ISD::SETLT; 603 CCs[RTLIB::OLT_F64] = ISD::SETLT; 604 CCs[RTLIB::OLT_F128] = ISD::SETLT; 605 CCs[RTLIB::OLE_F32] = ISD::SETLE; 606 CCs[RTLIB::OLE_F64] = ISD::SETLE; 607 CCs[RTLIB::OLE_F128] = ISD::SETLE; 608 CCs[RTLIB::OGT_F32] = ISD::SETGT; 609 CCs[RTLIB::OGT_F64] = ISD::SETGT; 610 CCs[RTLIB::OGT_F128] = ISD::SETGT; 611 CCs[RTLIB::UO_F32] = ISD::SETNE; 612 CCs[RTLIB::UO_F64] = ISD::SETNE; 613 CCs[RTLIB::UO_F128] = ISD::SETNE; 614 CCs[RTLIB::O_F32] = ISD::SETEQ; 615 CCs[RTLIB::O_F64] = ISD::SETEQ; 616 CCs[RTLIB::O_F128] = ISD::SETEQ; 617 } 618 619 /// NOTE: The constructor takes ownership of TLOF. 620 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm, 621 const TargetLoweringObjectFile *tlof) 622 : TM(tm), TD(TM.getDataLayout()), TLOF(*tlof) { 623 initActions(); 624 625 // Perform these initializations only once. 626 IsLittleEndian = TD->isLittleEndian(); 627 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize(0)); 628 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8; 629 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize 630 = MaxStoresPerMemmoveOptSize = 4; 631 UseUnderscoreSetJmp = false; 632 UseUnderscoreLongJmp = false; 633 SelectIsExpensive = false; 634 IntDivIsCheap = false; 635 Pow2DivIsCheap = false; 636 JumpIsExpensive = false; 637 PredictableSelectIsExpensive = false; 638 StackPointerRegisterToSaveRestore = 0; 639 ExceptionPointerRegister = 0; 640 ExceptionSelectorRegister = 0; 641 BooleanContents = UndefinedBooleanContent; 642 BooleanVectorContents = UndefinedBooleanContent; 643 SchedPreferenceInfo = Sched::ILP; 644 JumpBufSize = 0; 645 JumpBufAlignment = 0; 646 MinFunctionAlignment = 0; 647 PrefFunctionAlignment = 0; 648 PrefLoopAlignment = 0; 649 MinStackArgumentAlignment = 1; 650 InsertFencesForAtomic = false; 651 SupportJumpTables = true; 652 MinimumJumpTableEntries = 4; 653 654 InitLibcallNames(LibcallRoutineNames, TM); 655 InitCmpLibcallCCs(CmpLibcallCCs); 656 InitLibcallCallingConvs(LibcallCallingConvs); 657 } 658 659 TargetLoweringBase::~TargetLoweringBase() { 660 delete &TLOF; 661 } 662 663 void TargetLoweringBase::initActions() { 664 // All operations default to being supported. 665 memset(OpActions, 0, sizeof(OpActions)); 666 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 667 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 668 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 669 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 670 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); 671 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); 672 673 // Set default actions for various operations. 674 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { 675 // Default all indexed load / store to expand. 676 for (unsigned IM = (unsigned)ISD::PRE_INC; 677 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 678 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); 679 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); 680 } 681 682 // These operations default to expand. 683 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); 684 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); 685 } 686 687 // Most targets ignore the @llvm.prefetch intrinsic. 688 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 689 690 // ConstantFP nodes default to expand. Targets can either change this to 691 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 692 // to optimize expansions for certain constants. 693 setOperationAction(ISD::ConstantFP, MVT::f16, Expand); 694 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 695 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 696 setOperationAction(ISD::ConstantFP, MVT::f80, Expand); 697 setOperationAction(ISD::ConstantFP, MVT::f128, Expand); 698 699 // These library functions default to expand. 700 setOperationAction(ISD::FLOG , MVT::f16, Expand); 701 setOperationAction(ISD::FLOG2, MVT::f16, Expand); 702 setOperationAction(ISD::FLOG10, MVT::f16, Expand); 703 setOperationAction(ISD::FEXP , MVT::f16, Expand); 704 setOperationAction(ISD::FEXP2, MVT::f16, Expand); 705 setOperationAction(ISD::FFLOOR, MVT::f16, Expand); 706 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand); 707 setOperationAction(ISD::FCEIL, MVT::f16, Expand); 708 setOperationAction(ISD::FRINT, MVT::f16, Expand); 709 setOperationAction(ISD::FTRUNC, MVT::f16, Expand); 710 setOperationAction(ISD::FLOG , MVT::f32, Expand); 711 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 712 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 713 setOperationAction(ISD::FEXP , MVT::f32, Expand); 714 setOperationAction(ISD::FEXP2, MVT::f32, Expand); 715 setOperationAction(ISD::FFLOOR, MVT::f32, Expand); 716 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand); 717 setOperationAction(ISD::FCEIL, MVT::f32, Expand); 718 setOperationAction(ISD::FRINT, MVT::f32, Expand); 719 setOperationAction(ISD::FTRUNC, MVT::f32, Expand); 720 setOperationAction(ISD::FLOG , MVT::f64, Expand); 721 setOperationAction(ISD::FLOG2, MVT::f64, Expand); 722 setOperationAction(ISD::FLOG10, MVT::f64, Expand); 723 setOperationAction(ISD::FEXP , MVT::f64, Expand); 724 setOperationAction(ISD::FEXP2, MVT::f64, Expand); 725 setOperationAction(ISD::FFLOOR, MVT::f64, Expand); 726 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand); 727 setOperationAction(ISD::FCEIL, MVT::f64, Expand); 728 setOperationAction(ISD::FRINT, MVT::f64, Expand); 729 setOperationAction(ISD::FTRUNC, MVT::f64, Expand); 730 setOperationAction(ISD::FLOG , MVT::f128, Expand); 731 setOperationAction(ISD::FLOG2, MVT::f128, Expand); 732 setOperationAction(ISD::FLOG10, MVT::f128, Expand); 733 setOperationAction(ISD::FEXP , MVT::f128, Expand); 734 setOperationAction(ISD::FEXP2, MVT::f128, Expand); 735 setOperationAction(ISD::FFLOOR, MVT::f128, Expand); 736 setOperationAction(ISD::FNEARBYINT, MVT::f128, Expand); 737 setOperationAction(ISD::FCEIL, MVT::f128, Expand); 738 setOperationAction(ISD::FRINT, MVT::f128, Expand); 739 setOperationAction(ISD::FTRUNC, MVT::f128, Expand); 740 741 // Default ISD::TRAP to expand (which turns it into abort). 742 setOperationAction(ISD::TRAP, MVT::Other, Expand); 743 744 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 745 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 746 // 747 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 748 } 749 750 MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const { 751 return MVT::getIntegerVT(8*TD->getPointerSize(0)); 752 } 753 754 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const { 755 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 756 if (LHSTy.isVector()) 757 return LHSTy; 758 return getScalarShiftAmountTy(LHSTy); 759 } 760 761 /// canOpTrap - Returns true if the operation can trap for the value type. 762 /// VT must be a legal type. 763 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 764 assert(isTypeLegal(VT)); 765 switch (Op) { 766 default: 767 return false; 768 case ISD::FDIV: 769 case ISD::FREM: 770 case ISD::SDIV: 771 case ISD::UDIV: 772 case ISD::SREM: 773 case ISD::UREM: 774 return true; 775 } 776 } 777 778 779 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 780 unsigned &NumIntermediates, 781 MVT &RegisterVT, 782 TargetLoweringBase *TLI) { 783 // Figure out the right, legal destination reg to copy into. 784 unsigned NumElts = VT.getVectorNumElements(); 785 MVT EltTy = VT.getVectorElementType(); 786 787 unsigned NumVectorRegs = 1; 788 789 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 790 // could break down into LHS/RHS like LegalizeDAG does. 791 if (!isPowerOf2_32(NumElts)) { 792 NumVectorRegs = NumElts; 793 NumElts = 1; 794 } 795 796 // Divide the input until we get to a supported size. This will always 797 // end with a scalar if the target doesn't support vectors. 798 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { 799 NumElts >>= 1; 800 NumVectorRegs <<= 1; 801 } 802 803 NumIntermediates = NumVectorRegs; 804 805 MVT NewVT = MVT::getVectorVT(EltTy, NumElts); 806 if (!TLI->isTypeLegal(NewVT)) 807 NewVT = EltTy; 808 IntermediateVT = NewVT; 809 810 unsigned NewVTSize = NewVT.getSizeInBits(); 811 812 // Convert sizes such as i33 to i64. 813 if (!isPowerOf2_32(NewVTSize)) 814 NewVTSize = NextPowerOf2(NewVTSize); 815 816 MVT DestVT = TLI->getRegisterType(NewVT); 817 RegisterVT = DestVT; 818 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 819 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 820 821 // Otherwise, promotion or legal types use the same number of registers as 822 // the vector decimated to the appropriate level. 823 return NumVectorRegs; 824 } 825 826 /// isLegalRC - Return true if the value types that can be represented by the 827 /// specified register class are all legal. 828 bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const { 829 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); 830 I != E; ++I) { 831 if (isTypeLegal(*I)) 832 return true; 833 } 834 return false; 835 } 836 837 /// findRepresentativeClass - Return the largest legal super-reg register class 838 /// of the register class for the specified type and its associated "cost". 839 std::pair<const TargetRegisterClass*, uint8_t> 840 TargetLoweringBase::findRepresentativeClass(MVT VT) const { 841 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 842 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 843 if (!RC) 844 return std::make_pair(RC, 0); 845 846 // Compute the set of all super-register classes. 847 BitVector SuperRegRC(TRI->getNumRegClasses()); 848 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 849 SuperRegRC.setBitsInMask(RCI.getMask()); 850 851 // Find the first legal register class with the largest spill size. 852 const TargetRegisterClass *BestRC = RC; 853 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) { 854 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 855 // We want the largest possible spill size. 856 if (SuperRC->getSize() <= BestRC->getSize()) 857 continue; 858 if (!isLegalRC(SuperRC)) 859 continue; 860 BestRC = SuperRC; 861 } 862 return std::make_pair(BestRC, 1); 863 } 864 865 /// computeRegisterProperties - Once all of the register classes are added, 866 /// this allows us to compute derived properties we expose. 867 void TargetLoweringBase::computeRegisterProperties() { 868 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && 869 "Too many value types for ValueTypeActions to hold!"); 870 871 // Everything defaults to needing one register. 872 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 873 NumRegistersForVT[i] = 1; 874 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 875 } 876 // ...except isVoid, which doesn't need any registers. 877 NumRegistersForVT[MVT::isVoid] = 0; 878 879 // Find the largest integer register class. 880 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 881 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) 882 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 883 884 // Every integer value type larger than this largest register takes twice as 885 // many registers to represent as the previous ValueType. 886 for (unsigned ExpandedReg = LargestIntReg + 1; 887 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 888 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 889 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 890 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 891 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 892 TypeExpandInteger); 893 } 894 895 // Inspect all of the ValueType's smaller than the largest integer 896 // register to see which ones need promotion. 897 unsigned LegalIntReg = LargestIntReg; 898 for (unsigned IntReg = LargestIntReg - 1; 899 IntReg >= (unsigned)MVT::i1; --IntReg) { 900 MVT IVT = (MVT::SimpleValueType)IntReg; 901 if (isTypeLegal(IVT)) { 902 LegalIntReg = IntReg; 903 } else { 904 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 905 (const MVT::SimpleValueType)LegalIntReg; 906 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 907 } 908 } 909 910 // ppcf128 type is really two f64's. 911 if (!isTypeLegal(MVT::ppcf128)) { 912 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 913 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 914 TransformToType[MVT::ppcf128] = MVT::f64; 915 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 916 } 917 918 // Decide how to handle f128. If the target does not have native f128 support, 919 // expand it to i128 and we will be generating soft float library calls. 920 if (!isTypeLegal(MVT::f128)) { 921 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 922 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 923 TransformToType[MVT::f128] = MVT::i128; 924 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 925 } 926 927 // Decide how to handle f64. If the target does not have native f64 support, 928 // expand it to i64 and we will be generating soft float library calls. 929 if (!isTypeLegal(MVT::f64)) { 930 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 931 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 932 TransformToType[MVT::f64] = MVT::i64; 933 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 934 } 935 936 // Decide how to handle f32. If the target does not have native support for 937 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. 938 if (!isTypeLegal(MVT::f32)) { 939 if (isTypeLegal(MVT::f64)) { 940 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; 941 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; 942 TransformToType[MVT::f32] = MVT::f64; 943 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger); 944 } else { 945 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 946 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 947 TransformToType[MVT::f32] = MVT::i32; 948 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 949 } 950 } 951 952 // Loop over all of the vector value types to see which need transformations. 953 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 954 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 955 MVT VT = (MVT::SimpleValueType)i; 956 if (isTypeLegal(VT)) continue; 957 958 // Determine if there is a legal wider type. If so, we should promote to 959 // that wider vector type. 960 MVT EltVT = VT.getVectorElementType(); 961 unsigned NElts = VT.getVectorNumElements(); 962 if (NElts != 1 && !shouldSplitVectorElementType(EltVT)) { 963 bool IsLegalWiderType = false; 964 // First try to promote the elements of integer vectors. If no legal 965 // promotion was found, fallback to the widen-vector method. 966 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 967 MVT SVT = (MVT::SimpleValueType)nVT; 968 // Promote vectors of integers to vectors with the same number 969 // of elements, with a wider element type. 970 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() 971 && SVT.getVectorNumElements() == NElts && 972 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { 973 TransformToType[i] = SVT; 974 RegisterTypeForVT[i] = SVT; 975 NumRegistersForVT[i] = 1; 976 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 977 IsLegalWiderType = true; 978 break; 979 } 980 } 981 982 if (IsLegalWiderType) continue; 983 984 // Try to widen the vector. 985 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 986 MVT SVT = (MVT::SimpleValueType)nVT; 987 if (SVT.getVectorElementType() == EltVT && 988 SVT.getVectorNumElements() > NElts && 989 isTypeLegal(SVT)) { 990 TransformToType[i] = SVT; 991 RegisterTypeForVT[i] = SVT; 992 NumRegistersForVT[i] = 1; 993 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 994 IsLegalWiderType = true; 995 break; 996 } 997 } 998 if (IsLegalWiderType) continue; 999 } 1000 1001 MVT IntermediateVT; 1002 MVT RegisterVT; 1003 unsigned NumIntermediates; 1004 NumRegistersForVT[i] = 1005 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates, 1006 RegisterVT, this); 1007 RegisterTypeForVT[i] = RegisterVT; 1008 1009 MVT NVT = VT.getPow2VectorType(); 1010 if (NVT == VT) { 1011 // Type is already a power of 2. The default action is to split. 1012 TransformToType[i] = MVT::Other; 1013 unsigned NumElts = VT.getVectorNumElements(); 1014 ValueTypeActions.setTypeAction(VT, 1015 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector); 1016 } else { 1017 TransformToType[i] = NVT; 1018 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1019 } 1020 } 1021 1022 // Determine the 'representative' register class for each value type. 1023 // An representative register class is the largest (meaning one which is 1024 // not a sub-register class / subreg register class) legal register class for 1025 // a group of value types. For example, on i386, i8, i16, and i32 1026 // representative would be GR32; while on x86_64 it's GR64. 1027 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { 1028 const TargetRegisterClass* RRC; 1029 uint8_t Cost; 1030 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i); 1031 RepRegClassForVT[i] = RRC; 1032 RepRegClassCostForVT[i] = Cost; 1033 } 1034 } 1035 1036 EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const { 1037 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1038 return getPointerTy(0).SimpleTy; 1039 } 1040 1041 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1042 return MVT::i32; // return the default value 1043 } 1044 1045 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1046 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1047 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1048 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1049 /// 1050 /// This method returns the number of registers needed, and the VT for each 1051 /// register. It also returns the VT and quantity of the intermediate values 1052 /// before they are promoted/expanded. 1053 /// 1054 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT, 1055 EVT &IntermediateVT, 1056 unsigned &NumIntermediates, 1057 MVT &RegisterVT) const { 1058 unsigned NumElts = VT.getVectorNumElements(); 1059 1060 // If there is a wider vector type with the same element type as this one, 1061 // or a promoted vector type that has the same number of elements which 1062 // are wider, then we should convert to that legal vector type. 1063 // This handles things like <2 x float> -> <4 x float> and 1064 // <4 x i1> -> <4 x i32>. 1065 LegalizeTypeAction TA = getTypeAction(Context, VT); 1066 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1067 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1068 if (isTypeLegal(RegisterEVT)) { 1069 IntermediateVT = RegisterEVT; 1070 RegisterVT = RegisterEVT.getSimpleVT(); 1071 NumIntermediates = 1; 1072 return 1; 1073 } 1074 } 1075 1076 // Figure out the right, legal destination reg to copy into. 1077 EVT EltTy = VT.getVectorElementType(); 1078 1079 unsigned NumVectorRegs = 1; 1080 1081 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we 1082 // could break down into LHS/RHS like LegalizeDAG does. 1083 if (!isPowerOf2_32(NumElts)) { 1084 NumVectorRegs = NumElts; 1085 NumElts = 1; 1086 } 1087 1088 // Divide the input until we get to a supported size. This will always 1089 // end with a scalar if the target doesn't support vectors. 1090 while (NumElts > 1 && !isTypeLegal( 1091 EVT::getVectorVT(Context, EltTy, NumElts))) { 1092 NumElts >>= 1; 1093 NumVectorRegs <<= 1; 1094 } 1095 1096 NumIntermediates = NumVectorRegs; 1097 1098 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts); 1099 if (!isTypeLegal(NewVT)) 1100 NewVT = EltTy; 1101 IntermediateVT = NewVT; 1102 1103 MVT DestVT = getRegisterType(Context, NewVT); 1104 RegisterVT = DestVT; 1105 unsigned NewVTSize = NewVT.getSizeInBits(); 1106 1107 // Convert sizes such as i33 to i64. 1108 if (!isPowerOf2_32(NewVTSize)) 1109 NewVTSize = NextPowerOf2(NewVTSize); 1110 1111 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1112 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1113 1114 // Otherwise, promotion or legal types use the same number of registers as 1115 // the vector decimated to the appropriate level. 1116 return NumVectorRegs; 1117 } 1118 1119 /// Get the EVTs and ArgFlags collections that represent the legalized return 1120 /// type of the given function. This does not require a DAG or a return value, 1121 /// and is suitable for use before any DAGs for the function are constructed. 1122 /// TODO: Move this out of TargetLowering.cpp. 1123 void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr, 1124 SmallVectorImpl<ISD::OutputArg> &Outs, 1125 const TargetLowering &TLI) { 1126 SmallVector<EVT, 4> ValueVTs; 1127 ComputeValueVTs(TLI, ReturnType, ValueVTs); 1128 unsigned NumValues = ValueVTs.size(); 1129 if (NumValues == 0) return; 1130 1131 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1132 EVT VT = ValueVTs[j]; 1133 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1134 1135 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1136 ExtendKind = ISD::SIGN_EXTEND; 1137 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1138 ExtendKind = ISD::ZERO_EXTEND; 1139 1140 // FIXME: C calling convention requires the return type to be promoted to 1141 // at least 32-bit. But this is not necessary for non-C calling 1142 // conventions. The frontend should mark functions whose return values 1143 // require promoting with signext or zeroext attributes. 1144 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { 1145 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32); 1146 if (VT.bitsLT(MinVT)) 1147 VT = MinVT; 1148 } 1149 1150 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT); 1151 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT); 1152 1153 // 'inreg' on function refers to return value 1154 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1155 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg)) 1156 Flags.setInReg(); 1157 1158 // Propagate extension type if any 1159 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt)) 1160 Flags.setSExt(); 1161 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt)) 1162 Flags.setZExt(); 1163 1164 for (unsigned i = 0; i < NumParts; ++i) 1165 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true, 0, 0)); 1166 } 1167 } 1168 1169 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1170 /// function arguments in the caller parameter area. This is the actual 1171 /// alignment, not its logarithm. 1172 unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const { 1173 return TD->getCallFrameTypeAlignment(Ty); 1174 } 1175 1176 //===----------------------------------------------------------------------===// 1177 // TargetTransformInfo Helpers 1178 //===----------------------------------------------------------------------===// 1179 1180 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1181 enum InstructionOpcodes { 1182 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1183 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1184 #include "llvm/IR/Instruction.def" 1185 }; 1186 switch (static_cast<InstructionOpcodes>(Opcode)) { 1187 case Ret: return 0; 1188 case Br: return 0; 1189 case Switch: return 0; 1190 case IndirectBr: return 0; 1191 case Invoke: return 0; 1192 case Resume: return 0; 1193 case Unreachable: return 0; 1194 case Add: return ISD::ADD; 1195 case FAdd: return ISD::FADD; 1196 case Sub: return ISD::SUB; 1197 case FSub: return ISD::FSUB; 1198 case Mul: return ISD::MUL; 1199 case FMul: return ISD::FMUL; 1200 case UDiv: return ISD::UDIV; 1201 case SDiv: return ISD::UDIV; 1202 case FDiv: return ISD::FDIV; 1203 case URem: return ISD::UREM; 1204 case SRem: return ISD::SREM; 1205 case FRem: return ISD::FREM; 1206 case Shl: return ISD::SHL; 1207 case LShr: return ISD::SRL; 1208 case AShr: return ISD::SRA; 1209 case And: return ISD::AND; 1210 case Or: return ISD::OR; 1211 case Xor: return ISD::XOR; 1212 case Alloca: return 0; 1213 case Load: return ISD::LOAD; 1214 case Store: return ISD::STORE; 1215 case GetElementPtr: return 0; 1216 case Fence: return 0; 1217 case AtomicCmpXchg: return 0; 1218 case AtomicRMW: return 0; 1219 case Trunc: return ISD::TRUNCATE; 1220 case ZExt: return ISD::ZERO_EXTEND; 1221 case SExt: return ISD::SIGN_EXTEND; 1222 case FPToUI: return ISD::FP_TO_UINT; 1223 case FPToSI: return ISD::FP_TO_SINT; 1224 case UIToFP: return ISD::UINT_TO_FP; 1225 case SIToFP: return ISD::SINT_TO_FP; 1226 case FPTrunc: return ISD::FP_ROUND; 1227 case FPExt: return ISD::FP_EXTEND; 1228 case PtrToInt: return ISD::BITCAST; 1229 case IntToPtr: return ISD::BITCAST; 1230 case BitCast: return ISD::BITCAST; 1231 case ICmp: return ISD::SETCC; 1232 case FCmp: return ISD::SETCC; 1233 case PHI: return 0; 1234 case Call: return 0; 1235 case Select: return ISD::SELECT; 1236 case UserOp1: return 0; 1237 case UserOp2: return 0; 1238 case VAArg: return 0; 1239 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1240 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1241 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1242 case ExtractValue: return ISD::MERGE_VALUES; 1243 case InsertValue: return ISD::MERGE_VALUES; 1244 case LandingPad: return 0; 1245 } 1246 1247 llvm_unreachable("Unknown instruction type encountered!"); 1248 } 1249 1250 std::pair<unsigned, MVT> 1251 TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const { 1252 LLVMContext &C = Ty->getContext(); 1253 EVT MTy = getValueType(Ty); 1254 1255 unsigned Cost = 1; 1256 // We keep legalizing the type until we find a legal kind. We assume that 1257 // the only operation that costs anything is the split. After splitting 1258 // we need to handle two types. 1259 while (true) { 1260 LegalizeKind LK = getTypeConversion(C, MTy); 1261 1262 if (LK.first == TypeLegal) 1263 return std::make_pair(Cost, MTy.getSimpleVT()); 1264 1265 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger) 1266 Cost *= 2; 1267 1268 // Keep legalizing the type. 1269 MTy = LK.second; 1270 } 1271 } 1272 1273 //===----------------------------------------------------------------------===// 1274 // Loop Strength Reduction hooks 1275 //===----------------------------------------------------------------------===// 1276 1277 /// isLegalAddressingMode - Return true if the addressing mode represented 1278 /// by AM is legal for this target, for a load/store of the specified type. 1279 bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM, 1280 Type *Ty) const { 1281 // The default implementation of this implements a conservative RISCy, r+r and 1282 // r+i addr mode. 1283 1284 // Allows a sign-extended 16-bit immediate field. 1285 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 1286 return false; 1287 1288 // No global is ever allowed as a base. 1289 if (AM.BaseGV) 1290 return false; 1291 1292 // Only support r+r, 1293 switch (AM.Scale) { 1294 case 0: // "r+i" or just "i", depending on HasBaseReg. 1295 break; 1296 case 1: 1297 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 1298 return false; 1299 // Otherwise we have r+r or r+i. 1300 break; 1301 case 2: 1302 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 1303 return false; 1304 // Allow 2*r as r+r. 1305 break; 1306 } 1307 1308 return true; 1309 } 1310
