| /external/qemu/target-mips/ |
| helper.c | 291 } lui, lw, srl; member in struct:__anon27394
295 {0x00, 0x3c1b0000, 0xffff0000}, /* 0x3c1b803f : lui k1,%hi(pgd_current_p) */
301 {0x00, 0x3c1b0000, 0xffff0000}, /* 0x3c1b803f : lui k1,%hi(pgd_current_p) */
311 lui_ins = ldl_phys(ebase + handlers[i].lui.off);
314 if (((lui_ins & handlers[i].lui.mask) == handlers[i].lui.op) &&
|
| /external/chromium_org/v8/src/mips/ |
| assembler-mips.cc | 208 // specially coded on MIPS means that it is a lui/ori instruction, and that is
558 return opcode == LUI;
1456 void Assembler::lui(Register rd, int32_t j) { function in class:v8::Assembler
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.cc | 182 // specially coded on MIPS means that it is a lui/ori instruction, and that is
567 return opcode == LUI;
1449 void Assembler::lui(Register rd, int32_t j) { function in class:v8::Assembler
[all...] |
