/dalvik/vm/compiler/template/ia32/ |
header.S | 23 #define rINST %ebx
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/dalvik/vm/compiler/template/armv5te/ |
header.S | 65 r7 rINST first 16-bit code unit of current instruction 77 #define rINST r7
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/dalvik/vm/compiler/template/out/ |
CompilerTemplateAsm-ia32.S | 30 #define rINST %ebx
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CompilerTemplateAsm-armv5te.S | 72 r7 rINST first 16-bit code unit of current instruction 84 #define rINST r7 [all...] |
CompilerTemplateAsm-armv7-a-neon.S | 72 r7 rINST first 16-bit code unit of current instruction 84 #define rINST r7 [all...] |
CompilerTemplateAsm-armv7-a.S | 72 r7 rINST first 16-bit code unit of current instruction 84 #define rINST r7 [all...] |
CompilerTemplateAsm-armv5te-vfp.S | 72 r7 rINST first 16-bit code unit of current instruction 84 #define rINST r7 [all...] |
CompilerTemplateAsm-mips.S | 49 s4 rINST first 16-bit code unit of current instruction 123 #define rINST s4 162 #define FETCH_INST() lhu rINST, (rPC) 164 #define FETCH_ADVANCE_INST(_count) lhu rINST, (_count*2)(rPC); \ 168 lhu rINST, (rPC) 185 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF 217 #define GET_OPA(rd) srl rd, rINST, 8 223 #define GET_OPB(rd) srl rd, rINST, 12 738 la rINST, .LdvmICHitCount 742 lw t2, 0(rINST) [all...] |
/dalvik/vm/mterp/armv5te/ |
header.S | 60 r7 rINST first 16-bit code unit of current instruction 72 #define rINST r7 104 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 106 #define FETCH_INST() ldrh rINST, [rPC] 120 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 124 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 134 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 139 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 160 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255
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/dalvik/vm/mterp/x86/ |
header.S | 71 #define rINST %ebx 176 movzwl (rPC),rINST 200 movzwl \_count*2(rPC),rINST 208 movzwl (rPC,\_reg,2),rINST 227 movzbl rINSTbh,rINST 236 movzbl 1(rPC),rINST
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/dalvik/vm/mterp/out/ |
InterpAsm-x86.S | 78 #define rINST %ebx 183 movzwl (rPC),rINST 207 movzwl \_count*2(rPC),rINST 215 movzwl (rPC,\_reg,2),rINST 234 movzbl rINSTbh,rINST 243 movzbl 1(rPC),rINST 343 shrl $4,rINST # rINST<- B 344 GET_VREG_R rINST rINST [all...] |
InterpAsm-armv5te-vfp.S | 67 r7 rINST first 16-bit code unit of current instruction 79 #define rINST r7 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 113 #define FETCH_INST() ldrh rINST, [rPC] 127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255 315 FETCH_INST() @ load rINST from rP [all...] |
InterpAsm-armv5te.S | 67 r7 rINST first 16-bit code unit of current instruction 79 #define rINST r7 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 113 #define FETCH_INST() ldrh rINST, [rPC] 127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255 315 FETCH_INST() @ load rINST from rP [all...] |
InterpAsm-armv7-a-neon.S | 67 r7 rINST first 16-bit code unit of current instruction 79 #define rINST r7 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 113 #define FETCH_INST() ldrh rINST, [rPC] 127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255 329 FETCH_INST() @ load rINST from rP [all...] |
InterpAsm-armv7-a.S | 67 r7 rINST first 16-bit code unit of current instruction 79 #define rINST r7 111 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 113 #define FETCH_INST() ldrh rINST, [rPC] 127 #define FETCH_ADVANCE_INST(_count) ldrh rINST, [rPC, #((_count)*2)]! 131 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 141 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 146 #define FETCH_ADVANCE_INST_RB(_reg) ldrh rINST, [rPC, _reg]! 167 #define GET_INST_OPCODE(_reg) and _reg, rINST, #255 329 FETCH_INST() @ load rINST from rP [all...] |
InterpAsm-mips.S | 30 s4 rINST first 16-bit code unit of current instruction 39 #define rINST s4 84 #define FETCH_INST() lhu rINST, (rPC) 86 #define FETCH_ADVANCE_INST(_count) lhu rINST, ((_count)*2)(rPC); \ 94 lhu rINST, (rPC) 111 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF 147 #define GET_OPA(rd) srl rd, rINST, 8 151 #define GET_OPA4(rd) ext rd, rINST, 8, 4 153 #define GET_OPB(rd) srl rd, rINST, 12 446 FETCH_INST() # load rINST from rP [all...] |
/dalvik/vm/mterp/mips/ |
header.S | 23 s4 rINST first 16-bit code unit of current instruction 32 #define rINST s4 77 #define FETCH_INST() lhu rINST, (rPC) 79 #define FETCH_ADVANCE_INST(_count) lhu rINST, ((_count)*2)(rPC); \ 87 lhu rINST, (rPC) 104 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF 140 #define GET_OPA(rd) srl rd, rINST, 8 144 #define GET_OPA4(rd) ext rd, rINST, 8, 4 146 #define GET_OPB(rd) srl rd, rINST, 12
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/dalvik/vm/compiler/template/mips/ |
header.S | 42 s4 rINST first 16-bit code unit of current instruction 116 #define rINST s4 155 #define FETCH_INST() lhu rINST, (rPC) 157 #define FETCH_ADVANCE_INST(_count) lhu rINST, (_count*2)(rPC); \ 161 lhu rINST, (rPC) 178 #define GET_INST_OPCODE(rd) and rd, rINST, 0xFF 210 #define GET_OPA(rd) srl rd, rINST, 8 216 #define GET_OPB(rd) srl rd, rINST, 12
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/dalvik/vm/compiler/codegen/mips/ |
MipsLIR.h | 33 * s2 (rINST) is scratch for Jit 342 #define rINST r_S4
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