| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.h | 36 ARMCC::CondCodes Pred = ARMCC::AL,
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| Thumb1RegisterInfo.h | 42 ARMCC::CondCodes Pred = ARMCC::AL,
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| Thumb2RegisterInfo.cpp | 39 ARMCC::CondCodes Pred, unsigned PredReg,
50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
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| Thumb2ITBlockPass.cpp | 43 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
105 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
153 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
170 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
171 if (CC == ARMCC::AL) {
193 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
206 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg)
[all...] |
| Thumb2InstrInfo.h | 70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| ARMBaseInstrInfo.h | 77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
80 : ARMCC::AL;
323 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
366 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
387 ARMCC::CondCodes Pred, unsigned PredReg,
393 ARMCC::CondCodes Pred, unsigned PredReg,
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| ARMAsmPrinter.cpp | [all...] |
| ARMBaseRegisterInfo.h | 166 ARMCC::CondCodes Pred = ARMCC::AL,
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| ARMBaseInstrInfo.cpp | 161 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
410 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
423 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
431 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
432 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
442 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
449 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
480 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm()
[all...] |
| Thumb2InstrInfo.cpp | 40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
62 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
64 if (CC != ARMCC::AL)
72 if (CC != ARMCC::AL) {
110 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
215 ARMCC::CondCodes Pred, unsigned PredReg,
439 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
610 ARMCC::CondCodes
614 return ARMCC::AL;
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| ARMInstrInfo.cpp | 40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
46 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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| Thumb1InstrInfo.cpp | 33 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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| Thumb2SizeReduction.cpp | 153 bool is2Addr, ARMCC::CondCodes Pred,
294 bool is2Addr, ARMCC::CondCodes Pred,
298 if (Pred == ARMCC::AL) {
549 if (MI->getOperand(3).getImm() != ARMCC::AL)
584 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
688 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
690 if (Pred != ARMCC::AL) {
785 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
787 if (Pred != ARMCC::AL) {
[all...] |
| ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
108 ARMCC::CondCodes Pred,
115 ARMCC::CondCodes Pred, unsigned PredReg,
285 int Opcode, ARMCC::CondCodes Pred,
371 ARMCC::CondCodes Pred, unsigned PredReg,
448 ARMCC::CondCodes Pred, unsigned PredReg,
531 ARMCC::CondCodes Pred, unsigned PredReg) {
564 ARMCC::CondCodes Pred, unsigned PredReg) {
719 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
872 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg)
[all...] |
| ARMConstantIslandPass.cpp | [all...] |
| ARMISelLowering.h | 549 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
570 ARMCC::CondCodes CC = ARMCC::AL) const;
575 ARMCC::CondCodes Cond) const;
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| ARMFastISel.cpp | [all...] |
| ARMBaseRegisterInfo.cpp | 389 ARMCC::CondCodes Pred,
742 ARMCC::CondCodes Pred = (PIdx == -1)
743 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
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| ARMFrameLowering.cpp | 123 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
332 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
397 ARMCC::AL, 0, TII);
409 ARMCC::AL, 0, TII);
418 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
460 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
[all...] |
| ARMISelLowering.cpp | [all...] |
| MLxExpansionPass.cpp | 283 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
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| Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg,
126 ARMCC::AL, 0, MIFlags);
374 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 26 namespace ARMCC {
66 } // namespace ARMCC
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
70 case ARMCC::EQ: return "eq";
71 case ARMCC::NE: return "ne";
72 case ARMCC::HS: return "hs";
73 case ARMCC::LO: return "lo";
74 case ARMCC::MI: return "mi";
75 case ARMCC::PL: return "pl";
76 case ARMCC::VS: return "vs"
[all...] |
| ARMMCTargetDesc.cpp | 237 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
244 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 70 ARMCC::CondCodes Cond; // Condition for IT block.
322 ARMCC::CondCodes Val;
535 ARMCC::CondCodes getCondCode() const {
[all...] |
