| /dalvik/vm/compiler/codegen/arm/ |
| Codegen.h | 38 static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
42 static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
46 static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir);
49 static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir);
52 static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir);
[all...] |
| CodegenDriver.cpp | 47 static bool genConversionCall(CompilationUnit *cUnit, MIR *mir, void *funct,
58 rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
61 rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
69 rlDest = dvmCompilerGetDest(cUnit, mir, 0);
74 rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1);
81 static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
88 switch (mir->dalvikInsn.opcode) {
127 static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir
4207 MIR *mir; local
[all...] |
| /dalvik/vm/compiler/codegen/arm/FP/ |
| ThumbPortableFP.cpp | 18 static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
22 static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
26 static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir);
28 static bool handleExecuteInlineC(CompilationUnit *cUnit, MIR *mir);
30 static bool genConversion(CompilationUnit *cUnit, MIR *mir)
[all...] |
| ThumbVFP.cpp | 45 static bool genInlineSqrt(CompilationUnit *cUnit, MIR *mir)
47 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
64 static bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir,
74 switch (mir->dalvikInsn.opcode) {
94 return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
110 static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir,
116 switch (mir->dalvikInsn.opcode)
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| Thumb2VFP.cpp | 17 static bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir,
28 switch (mir->dalvikInsn.opcode) {
48 return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1,
63 static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir,
70 switch (mir->dalvikInsn.opcode) {
90 return genArithOpDoublePortable(cUnit, mir, rlDest, rlSrc1,
111 static bool genConversion(CompilationUnit *cUnit, MIR *mir)
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Codegen.h | 38 static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
42 static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
46 static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir);
48 static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir);
50 static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir);
[all...] |
| Ralloc.h | 77 static inline int dvmCompilerSSASrc(MIR *mir, int num)
79 assert(mir->ssaRep->numUses > num);
80 return mir->ssaRep->uses[num];
129 extern RegLocation dvmCompilerGetSrcWide(CompilationUnit *cUnit, MIR *mir,
132 extern RegLocation dvmCompilerGetDestWide(CompilationUnit *cUnit, MIR *mir,
135 extern RegLocation dvmCompilerGetSrc(CompilationUnit *cUnit, MIR *mir, int num)
[all...] |
| /dalvik/vm/compiler/ |
| InlineTransformation.cpp | 39 MIR *invokeMIR,
45 MIR *moveResultMIR = moveResultBB->firstMIRInsn;
46 MIR *newGetterMIR = (MIR *)dvmCompilerNew(sizeof(MIR), true);
110 MIR *invokeMIRSlow = (MIR *)dvmCompilerNew(sizeof(MIR), true);
139 MIR *invokeMIR,
144 MIR *newSetterMIR = (MIR *)dvmCompilerNew(sizeof(MIR), true)
[all...] |
| CompilerIR.h | 128 typedef struct MIR {
132 struct MIR *prev;
133 struct MIR *next;
143 } MIR;
164 MIR *firstMIRInsn;
165 MIR *lastMIRInsn;
291 void dvmCompilerAppendMIR(BasicBlock *bb, MIR *mir);
293 void dvmCompilerPrependMIR(BasicBlock *bb, MIR *mir);
[all...] |
| IntermediateRep.cpp | 31 /* Insert an MIR instruction to the end of a basic block */
32 void dvmCompilerAppendMIR(BasicBlock *bb, MIR *mir)
36 bb->lastMIRInsn = bb->firstMIRInsn = mir;
37 mir->prev = mir->next = NULL;
39 bb->lastMIRInsn->next = mir;
40 mir->prev = bb->lastMIRInsn;
41 mir->next = NULL;
42 bb->lastMIRInsn = mir;
[all...] |
| Loop.cpp | 206 MIR *branch = loopBackBlock->lastMIRInsn;
346 MIR *mir; local
349 for (mir = loopBody->firstMIRInsn; mir; mir = mir->next) {
350 DecodedInstruction *dInsn = &mir->dalvikInsn;
352 dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode];
354 /* Skip extended MIR instructions *
[all...] |
| Ralloc.cpp | 29 MIR *mir; local
33 for (mir = bb->firstMIRInsn; mir; mir = mir->next) {
34 SSARepresentation *ssaRep = mir->ssaRep;
|
| /dalvik/vm/compiler/codegen/arm/armv7-a-neon/ |
| MethodCodegenDriver.cpp | 40 static void genMethodInflateAndPunt(CompilationUnit *cUnit, MIR *mir,
69 loadConstant(cUnit, currentPC, (int) (cUnit->method->insns + mir->offset));
98 genPuntToInterp(cUnit, mir->offset);
108 static bool handleMethodFmt10t_Fmt20t_Fmt30t(CompilationUnit *cUnit, MIR *mir,
112 bool backwardBranch = (bb->taken->startOffset <= mir->offset);
115 genSuspendPoll(cUnit, mir);
123 static bool handleMethodFmt10x(CompilationUnit *cUnit, MIR *mir)
[all...] |
| /art/compiler/dex/ |
| mir_graph.h | 215 * Normalized use/def for a MIR operation using SSA names rather than vregs. Note that
235 struct MIR {
239 int m_unit_index; // From which method was this MIR included
240 MIR* prev;
241 MIR* next;
246 MIR* throw_insn;
267 MIR* first_mir_insn;
268 MIR* last_mir_insn;
356 * Parse dex method and add MIR at current insert point. Returns id (which is
499 RegLocation GetRawSrc(MIR* mir, int num)
[all...] |
| mir_optimization.cc | 40 MIR* mir; local
42 for (mir = bb->first_mir_insn; mir != NULL; mir = mir->next) {
43 int df_attributes = oat_data_flow_attributes_[mir->dalvikInsn.opcode];
45 DecodedInstruction *d_insn = &mir->dalvikInsn;
57 SetConstant(mir->ssa_rep->defs[0], vB);
60 SetConstant(mir->ssa_rep->defs[0], vB << 16)
566 MIR* mir = bb->last_mir_insn; local
[all...] |
| mir_graph.cc | 133 MIR* insn = orig_block->first_mir_insn;
278 BasicBlock* MIRGraph::ProcessCanBranch(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
344 void MIRGraph::ProcessCanSwitch(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
420 BasicBlock* MIRGraph::ProcessCanThrow(BasicBlock* cur_block, MIR* insn, int cur_offset, int width,
484 * pseudo exception edge MIR. Note also that this new block is
493 MIR* new_insn = static_cast<MIR*>(arena_->Alloc(sizeof(MIR), ArenaAllocator::kAllocMIR));
512 // TODO: will need to snapshot stack image and use that as the mir context identification.
579 MIR *insn = static_cast<MIR *>(arena_->Alloc(sizeof(MIR), ArenaAllocator::kAllocMIR))
739 const MIR *mir; local
[all...] |
| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 122 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
123 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
124 void GenSelect(BasicBlock* bb, MIR* mir);
133 void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
134 void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src)
[all...] |
| call_arm.cc | 82 void ArmMir2Lir::LockLiveArgs(MIR* mir) {
85 for (int i = 0; i < mir->ssa_rep->num_uses; i++) {
86 int v_reg = mir_graph_->SRegToVReg(mir->ssa_rep->uses[i]);
94 /* Find the next MIR, which may be in a following basic block */
96 MIR* ArmMir2Lir::GetNextMir(BasicBlock** p_bb, MIR* mir) {
98 MIR* orig_mir = mir;
[all...] |
| /dalvik/vm/compiler/codegen/ |
| Ralloc.h | 73 static inline int dvmCompilerSSASrc(MIR *mir, int num)
75 assert(mir->ssaRep->numUses > num);
76 return mir->ssaRep->uses[num];
125 extern RegLocation dvmCompilerGetSrcWide(CompilationUnit *cUnit, MIR *mir,
128 extern RegLocation dvmCompilerGetDestWide(CompilationUnit *cUnit, MIR *mir,
131 extern RegLocation dvmCompilerGetSrc(CompilationUnit *cUnit, MIR *mir, int num)
[all...] |
| /art/compiler/dex/portable/ |
| mir_to_gbc.h | 33 struct MIR;
110 void ConvertCompareAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
112 void ConvertCompareZeroAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
128 void ConvertInvoke(BasicBlock* bb, MIR* mir, InvokeType invoke_type,
161 bool ConvertMIRNode(MIR* mir, BasicBlock* bb, ::llvm::BasicBlock* llvm_bb);
165 void ConvertExtendedMIR(BasicBlock* bb, MIR* mir, ::llvm::BasicBlock* llvm_bb)
[all...] |
| /art/compiler/dex/quick/mips/ |
| codegen_mips.h | 123 void GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, bool is_double);
124 void GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir);
125 void GenSelect(BasicBlock* bb, MIR* mir);
134 void GenPackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src);
135 void GenSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src)
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| Gen.cpp | 124 static void genLong3Addr(CompilationUnit *cUnit, MIR *mir, OpKind firstOp,
133 genInterpSingleStep(cUnit, mir);
186 static ArmLIR *genExportPC(CompilationUnit *cUnit, MIR *mir)
192 res = loadConstant(cUnit, rDPC, (int) (cUnit->method->insns + mir->offset));
199 static void genMonitor(CompilationUnit *cUnit, MIR *mir)
201 genMonitorPortable(cUnit, mir);
204 static void genCmpLong(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest
[all...] |
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Gen.cpp | 132 static void genLong3Addr(CompilationUnit *cUnit, MIR *mir, OpKind firstOp,
143 genInterpSingleStep(cUnit, mir);
218 static MipsLIR *genExportPC(CompilationUnit *cUnit, MIR *mir)
224 res = loadConstant(cUnit, rDPC, (int) (cUnit->method->insns + mir->offset));
230 static void genMonitor(CompilationUnit *cUnit, MIR *mir)
232 genMonitorPortable(cUnit, mir);
235 static void genCmpLong(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest
[all...] |
| /dalvik/vm/compiler/codegen/mips/FP/ |
| MipsFP.cpp | 44 static bool genInlineSqrt(CompilationUnit *cUnit, MIR *mir)
46 RegLocation rlSrc = dvmCompilerGetSrcWide(cUnit, mir, 0, 1);
67 static bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir,
79 switch (mir->dalvikInsn.opcode) {
99 return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
118 switch (mir->dalvikInsn.opcode) {
138 return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
157 static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Gen.cpp | 125 static void genLong3Addr(CompilationUnit *cUnit, MIR *mir, OpKind firstOp,
198 static ArmLIR *genExportPC(CompilationUnit *cUnit, MIR *mir)
203 res = loadConstant(cUnit, rDPC, (int) (cUnit->method->insns + mir->offset));
237 static void genMonitorEnter(CompilationUnit *cUnit, MIR *mir)
239 RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0);
249 genNullCheck(cUnit, rlSrc.sRegLow, r1, mir->offset, NULL);
268 loadConstant(cUnit, r3, (int) (cUnit->method->insns + mir->offset))
[all...] |
