| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 360 APInt NewMask = DemandedMask;
375 // just set the NewMask to all bits.
376 NewMask = APInt::getAllOnesValue(BitWidth);
403 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
407 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
411 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
415 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
422 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
[all...] |
| LegalizeDAG.cpp | 200 SmallVector<int, 8> NewMask;
205 NewMask.push_back(-1);
207 NewMask.push_back(Idx * NumEltsGrowth + j);
210 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
211 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
[all...] |
| LegalizeVectorTypes.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 359 APInt NewMask = ~(LHSKnownOne & RHSKnownOne & DemandedMask);
362 ConstantInt::get(I->getType(), NewMask & AndRHS->getValue());
367 ConstantInt::get(I->getType(), NewMask & XorRHS->getValue());
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 826 SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT);
827 N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 789 SDValue NewMask = DAG.getConstant(0xff, VT);
791 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
802 InsertDAGNode(DAG, N, NewMask);
836 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
837 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
845 InsertDAGNode(DAG, N, NewMask);
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
