| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 182 SmallVector<CCValAssign, 16> RVLocs;
186 DAG.getTarget(), RVLocs, *DAG.getContext());
197 for (unsigned i = 0; i != RVLocs.size(); ++i) {
198 CCValAssign &VA = RVLocs[i];
243 SmallVector<CCValAssign, 16> RVLocs;
247 DAG.getTarget(), RVLocs, *DAG.getContext());
260 for (unsigned i = 0; i != RVLocs.size(); ++i) {
261 CCValAssign &VA = RVLocs[i];
287 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg())
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 415 SmallVector<CCValAssign, 16> RVLocs;
423 getTargetMachine(), RVLocs, *DAG.getContext());
432 for (unsigned i = 0; i != RVLocs.size(); ++i) {
433 CCValAssign &VA = RVLocs[i];
609 SmallVector<CCValAssign, 16> RVLocs;
611 getTargetMachine(), RVLocs, *DAG.getContext());
616 for (unsigned i = 0; i != RVLocs.size(); ++i) {
617 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
618 RVLocs[i].getValVT(), InFlag).getValue(1);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 308 SmallVector<CCValAssign, 16> RVLocs;
312 getTargetMachine(), RVLocs, *DAG.getContext());
321 for (unsigned i = 0; i != RVLocs.size(); ++i) {
322 CCValAssign &VA = RVLocs[i];
360 SmallVector<CCValAssign, 16> RVLocs;
363 getTargetMachine(), RVLocs, *DAG.getContext());
368 for (unsigned i = 0; i != RVLocs.size(); ++i) {
370 RVLocs[i].getLocReg(),
371 RVLocs[i].getValVT(), InFlag).getValue(1);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
