| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 202 { ISD::SDIV, MVT::v32i8, 32*20 },
203 { ISD::SDIV, MVT::v16i16, 16*20 },
204 { ISD::SDIV, MVT::v8i32, 8*20 },
205 { ISD::SDIV, MVT::v4i64, 4*20 },
279 { ISD::SDIV, MVT::v16i8, 16*20 },
280 { ISD::SDIV, MVT::v8i16, 8*20 },
281 { ISD::SDIV, MVT::v4i32, 4*20 },
282 { ISD::SDIV, MVT::v2i64, 2*20 },
|
| X86ISelLowering.cpp | 420 setOperationAction(ISD::SDIV, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 150 case ISD::SDIV:
161 if (N->getOpcode() == ISD::SDIV) {
171 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 488 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost},
492 { ISD::SDIV, MVT::v2i32, 2 * FunctionCallDivCost},
496 { ISD::SDIV, MVT::v4i16, ReciprocalDivCost},
500 { ISD::SDIV, MVT::v8i8, ReciprocalDivCost},
505 { ISD::SDIV, MVT::v2i64, 2 * FunctionCallDivCost},
509 { ISD::SDIV, MVT::v4i32, 4 * FunctionCallDivCost},
513 { ISD::SDIV, MVT::v8i16, 8 * FunctionCallDivCost},
517 { ISD::SDIV, MVT::v16i8, 16 * FunctionCallDivCost},
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 176 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 89 case ISD::SDIV: return LowerSDIV(Op, DAG);
|
| AMDILISelLowering.cpp | 123 setOperationAction(ISD::SDIV, VT, Custom);
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
|
| /external/llvm/lib/Target/Mips/ |
| MipsCodeEmitter.cpp | 330 expandACCInstr(MI, MBB, Mips::SDIV);
|
| MipsISelLowering.cpp | 287 setOperationAction(ISD::SDIV, MVT::i32, Expand);
291 setOperationAction(ISD::SDIV, MVT::i64, Expand);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.cpp | 89 case ISD::SDIV: return LowerSDIV(Op, DAG);
|
| AMDILISelLowering.cpp | 123 setOperationAction(ISD::SDIV, VT, Custom);
181 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
|
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 112 setOperationAction(ISD::SDIV, VT, Custom);
165 setOperationAction(ISD::SDIV, MVT::v2i64, Expand);
|
| AMDGPUISelLowering.cpp | 180 case ISD::SDIV: return LowerSDIV(Op, DAG);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 157 case ISD::SDIV: return "sdiv";
|
| FastISel.cpp | 408 // Transform "sdiv exact X, 8" -> "sra X, 3".
409 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
[all...] |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
196 case ISD::SDIV:
|
| LegalizeVectorTypes.cpp | 107 case ISD::SDIV:
560 case ISD::SDIV:
[all...] |
| LegalizeDAG.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 109 case ISD::SDIV:
[all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 157 setOperationAction(ISD::SDIV, MVT::i8, Expand);
163 setOperationAction(ISD::SDIV, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 770 case ISD::SDIV:
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
