| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 370 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
375 SIGN_EXTEND_INREG,
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 108 //FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
|
| AMDGPUISelLowering.cpp | 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
|
| /external/llvm/lib/Target/R600/ |
| AMDILISelLowering.cpp | 97 //FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
99 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
194 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
201 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
|
| AMDGPUISelLowering.cpp | 182 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 108 //FIXME: SIGN_EXTEND_INREG is not meaningful for floating point types
110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);
|
| AMDGPUISelLowering.cpp | 92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 64 // Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
248 case ISD::SIGN_EXTEND_INREG:
286 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG)
|
| LegalizeIntegerTypes.cpp | 72 case ISD::SIGN_EXTEND_INREG:
399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
464 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
553 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
685 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
[all...] |
| SelectionDAGDumper.cpp | 214 case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";
|
| LegalizeVectorTypes.cpp | 60 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
272 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
509 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
[all...] |
| LegalizeTypes.h | 204 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
[all...] |
| DAGCombiner.cpp | 776 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
788 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
[all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| TargetLowering.cpp | 734 case ISD::SIGN_EXTEND_INREG: {
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 141 // Some SIGN_EXTEND_INREG can be done using cvt instruction.
143 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
145 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
147 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 140 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 472 IndexOpcode == ISD::SIGN_EXTEND_INREG)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
367 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
368 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | [all...] |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 126 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
[all...] |
