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    Searched refs:Src0 (Results 1 - 7 of 7) sorted by null

  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 97 unsigned Src0 = MI.getOperand(1).getReg();
106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
152 .addReg(Src0)
  /external/mesa3d/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 97 unsigned Src0 = MI.getOperand(1).getReg();
106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
152 .addReg(Src0)
  /external/llvm/lib/Target/R600/
R600ExpandSpecialInstrs.cpp 81 MI.getOperand(1).getReg(), // src0
195 unsigned Src0 = BMI->getOperand(
196 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0))
201 (void) Src0;
203 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
205 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
247 unsigned Src0 = MI.getOperand(
248 TII->getOperandIdx(MI, AMDGPU::OpName::src0)).getReg();
260 Src0 = TRI.getSubReg(Src0, SubRegIndex)
    [all...]
R600InstrInfo.cpp 75 NewMI->getOperand(getOperandIdx(*NewMI, AMDGPU::OpName::src0))
194 AMDGPU::OpName::src0,
206 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
260 {AMDGPU::OpName::src0, AMDGPU::OpName::src0_sel},
484 //Todo : support shared src0 - src1 operand
    [all...]
  /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/
armCOMM_IDCT_s.h 663 Src0 EQU 7
673 qXj0 QN Src0.S16
683 dXj0lo DN (Src0*2).S16
684 dXj0hi DN (Src0*2+1).S16
876 XTR5 EQU Src0
    [all...]
  /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/
armCOMM_IDCT_s.h 669 Src0 EQU 7
679 qXj0 QN Src0.S16
689 dXj0lo DN (Src0*2).S16
690 dXj0hi DN (Src0*2+1).S16
882 XTR5 EQU Src0
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorTypes.cpp     [all...]

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