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    Searched refs:Srl (Results 1 - 5 of 5) sorted by null

  /art/compiler/utils/mips/
assembler_mips.h 244 void Srl(Register rd, Register rs, int shamt);
assembler_mips.cc 246 void MipsAssembler::Srl(Register rd, Register rs, int shamt) {
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  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 346 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
350 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
352 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
382 // Look for (and (srl X, c1), c2).
383 SDValue Srl = N1.getOperand(0);
385 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
404 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32
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  /external/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 776 if (Shift.getOpcode() != ISD::SRL ||
790 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
791 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
801 InsertDAGNode(DAG, N, Srl);
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X86ISelLowering.cpp 553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
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