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    Searched refs:ValueVT (Results 1 - 3 of 3) sorted by null

  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 93 MVT PartVT, EVT ValueVT, const Value *V);
97 /// larger then ValueVT then AssertOp can be used to specify whether the extra
98 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
102 unsigned NumParts, MVT PartVT, EVT ValueVT,
105 if (ValueVT.isVector())
107 PartVT, ValueVT, V);
115 if (ValueVT.isInteger()) {
117 unsigned ValueBits = ValueVT.getSizeInBits();
124 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
165 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &
    [all...]
FunctionLoweringInfo.cpp 231 EVT ValueVT = ValueVTs[Value];
232 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
234 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
  /external/llvm/lib/Target/R600/
R600ISelLowering.cpp     [all...]

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