| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| PPCBranchSelector.cpp | 168 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
170 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
172 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
174 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
176 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
|
| PPCFrameLowering.cpp | 143 .addImm(UsedRegMask);
147 .addImm(UsedRegMask);
152 .addImm(UsedRegMask >> 16);
156 .addImm(UsedRegMask >> 16);
161 .addImm(UsedRegMask >> 16);
165 .addImm(UsedRegMask >> 16);
169 .addImm(UsedRegMask & 0xFFFF);
427 .addImm(FPOffset)
433 .addImm(BPOffset)
439 .addImm(LROffset
[all...] |
| PPCFastISel.cpp | 167 .addImm(Imm);
173 .addImm(Hi);
176 .addReg(TmpReg).addImm(Lo);
181 .addImm(Hi);
220 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
228 TmpReg3).addReg(TmpReg2).addImm(Hi);
235 ResultReg).addReg(TmpReg3).addImm(Lo);
260 .addImm(CI->getSExtValue());
|
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
133 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
137 MIB.addImm(AM.Disp);
177 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
|
| /external/llvm/lib/Target/R600/ |
| R600ControlFlowFinalizer.cpp | 169 .addImm(0) // ADDR
170 .addImm(AluInstCount - 1); // COUNT
209 .addImm(LiteralPair0)
210 .addImm(LiteralPair1);
254 .addImm(literal0)
255 .addImm(literal2);
270 .addImm(CfCount);
284 .addImm(CfCount);
393 .addImm(1);
409 .addImm(Pair.first + 1)
[all...] |
| R600ISelLowering.cpp | 188 .addImm(EOP); // Set End of program bit
232 .addImm(SrcX)
233 .addImm(SrcY)
234 .addImm(SrcZ)
235 .addImm(SrcW)
236 .addImm(0)
237 .addImm(0)
238 .addImm(0)
239 .addImm(0)
240 .addImm(1
[all...] |
| R600EmitClauseMarkers.cpp | 207 .addImm(Address++) // ADDR
208 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
209 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].first) // KB1
210 .addImm(KCacheBanks.empty()?0:2) // KM0
211 .addImm((KCacheBanks.size() < 2)?0:2) // KM1
212 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].second) // KLINE0
213 .addImm((KCacheBanks.size() < 2)?0:KCacheBanks[1].second) // KLINE1
214 .addImm(AluInstCount) // COUNT
215 .addImm(1); // Enabled
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 100 HEXAGON_RESERVED_REG_1).addImm(Offset);
109 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
112 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
118 .addImm(0)
126 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
144 HEXAGON_RESERVED_REG_1).addImm(Offset);
152 .addImm(0);
157 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
161 .addImm(0);
167 HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset)
[all...] |
| HexagonSplitConst32AndConst64.cpp | 128 TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
130 TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
147 TII->get(Hexagon::LOi), DestLo).addImm(LowWord);
150 TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
153 TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
156 TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
|
| HexagonRegisterInfo.cpp | 178 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
185 dstReg).addReg(FrameReg).addImm(Offset);
207 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
214 resReg).addReg(FrameReg).addImm(Offset);
239 TII.get(Hexagon::CONST32_Int_Real), ResReg).addImm(Offset);
249 addImm(Offset);
258 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
|
| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 38 MCInstBuilder &addImm(int64_t Val) {
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 50 LocalReg).addImm(MF.getFunctionNumber());
57 LocalReg).addImm(MF.getFunctionNumber());
|
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| Thumb2RegisterInfo.cpp | 50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
| Thumb2InstrInfo.cpp | 146 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
160 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
187 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
201 MIB.addFrameIndex(FI).addImm(0).addMemOperand(MMO);
229 .addImm(NumBytes)
230 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
236 .addImm(NumBytes >> 16)
237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
246 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
252 .addImm((unsigned)Pred).addReg(PredReg).addReg(0
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 89 .addImm(0) // ABS
90 .addImm(1) // CLAMP
91 .addImm(0) // OMOD
92 .addImm(0); // NEG
104 .addImm(1) // ABS
105 .addImm(0) // CLAMP
106 .addImm(0) // OMOD
107 .addImm(0); // NEG
119 .addImm(0) // ABS
120 .addImm(0) // CLAM
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 89 .addImm(0) // ABS
90 .addImm(1) // CLAMP
91 .addImm(0) // OMOD
92 .addImm(0); // NEG
104 .addImm(1) // ABS
105 .addImm(0) // CLAMP
106 .addImm(0) // OMOD
107 .addImm(0); // NEG
119 .addImm(0) // ABS
120 .addImm(0) // CLAM
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 61 .addReg(SP::O6).addImm(NumBytes);
66 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
69 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
88 .addImm(Size);
118 .addReg(SP::O6).addImm(NumBytes);
123 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
126 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
|
| SparcInstrInfo.cpp | 198 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
240 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
242 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
325 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
328 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
331 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
334 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
357 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
360 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
363 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 195 .addImm(Offset);
201 .addImm(Offset);
206 .addImm(Offset);
223 .addImm(Offset);
229 .addImm(Offset);
234 .addImm(Offset);
254 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 113 addFrameIndex(FI).addImm(Offset)
129 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
180 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
185 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
202 MIB1.addImm(-4);
206 MIB2.addImm(-8);
210 MIB3.addImm(-12);
222 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
231 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
242 MIB1.addImm(-4)
[all...] |
| MipsLongBranch.cpp | 289 .addReg(Mips::SP).addImm(-8);
291 .addReg(Mips::SP).addImm(0);
295 .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
300 .addReg(Mips::AT).addImm(Lo);
304 .addReg(Mips::SP).addImm(0);
309 .addReg(Mips::SP).addImm(8));
336 .addReg(Mips::SP_64).addImm(-16);
338 .addReg(Mips::SP_64).addImm(0);
340 .addImm(Highest);
342 .addReg(Mips::AT_64).addImm(Higher)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 43 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 51 .addImm(0);
57 .addImm(0);
63 .addImm(A64SysReg::NZCV)
69 .addImm(A64SysReg::NZCV);
101 .addImm(0x1ff & -16);
106 .addImm(16);
116 .addImm(0);
409 .addImm(0)
454 .addImm(0)
616 .addImm(0xffff & Bits).addImm(0
[all...] |
