| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
127 MIB.addReg(AM.Base.Reg)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 103 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1);
105 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
108 .addReg(HEXAGON_RESERVED_REG_1)
109 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
112 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
114 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
117 .addReg(HEXAGON_RESERVED_REG_1)
119 .addReg(HEXAGON_RESERVED_REG_2);
123 HEXAGON_RESERVED_REG_2).addReg(SrcReg)
[all...] |
| HexagonSplitTFRCondSets.cpp | 115 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
119 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
135 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
140 addReg(MI->getOperand(1).getReg()).
145 addReg(MI->getOperand(1).getReg()).
161 addReg(MI->getOperand(1).getReg()).
166 addReg(MI->getOperand(1).getReg())
[all...] |
| HexagonRegisterInfo.cpp | 181 dstReg).addReg(FrameReg).addReg(dstReg);
185 dstReg).addReg(FrameReg).addImm(Offset);
210 resReg).addReg(FrameReg).addReg(resReg);
214 resReg).addReg(FrameReg).addImm(Offset);
241 TII.get(Hexagon::ADD_rr), ResReg).addReg(FrameReg).
242 addReg(ResReg);
248 TII.get(Hexagon::ADD_ri), ResReg).addReg(FrameReg).
261 dstReg).addReg(FrameReg).addReg(dstReg)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SILowerControlFlow.cpp | 140 .addReg(AMDGPU::EXEC);
157 .addReg(AMDGPU::EXEC);
166 .addReg(AMDGPU::VGPR0)
167 .addReg(AMDGPU::VGPR0)
168 .addReg(AMDGPU::VGPR0)
169 .addReg(AMDGPU::VGPR0);
182 .addReg(Vcc);
185 .addReg(AMDGPU::EXEC)
186 .addReg(Reg);
201 .addReg(Src); // Saved EXE
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx)
50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
| ARMExpandPseudoInsts.cpp | 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
466 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
468 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
470 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
472 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
522 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
[all...] |
| Thumb2InstrInfo.cpp | 122 .addReg(SrcReg, getKillRegState(KillSrc)));
145 .addReg(SrcReg, getKillRegState(isKill))
205 MIB.addReg(DestReg, RegState::ImplicitDefine);
230 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
235 .addReg(DestReg)
237 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
244 .addReg(BaseReg, RegState::Kill)
245 .addReg(DestReg, RegState::Kill)
246 .addImm((unsigned)Pred).addReg(PredReg).addReg(0
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 142 .addReg(SrcReg)
146 .addReg(SrcReg, RegState::Kill)
151 .addReg(SrcReg)
155 .addReg(SrcReg, RegState::Kill)
160 .addReg(SrcReg)
164 .addReg(SrcReg, RegState::Kill)
168 .addReg(DstReg, RegState::Kill)
421 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
426 .addReg(PPC::X31)
428 .addReg(PPC::X1)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 173 .addReg(FrameReg)
174 .addReg(ScratchReg, RegState::Kill);
178 .addReg(Reg, getKillRegState(isKill))
179 .addReg(FrameReg)
180 .addReg(ScratchReg, RegState::Kill);
184 .addReg(FrameReg)
185 .addReg(ScratchReg, RegState::Kill);
194 .addReg(FrameReg)
199 .addReg(Reg, getKillRegState(isKill))
200 .addReg(FrameReg
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 61 .addReg(SP::O6).addImm(NumBytes);
69 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
71 .addReg(SP::O6).addReg(SP::G1);
87 BuildMI(MBB, I, DL, TII.get(SP::ADDri), SP::O6).addReg(SP::O6)
104 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
105 .addReg(SP::G0);
118 .addReg(SP::O6).addImm(NumBytes);
126 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
128 .addReg(SP::O6).addReg(SP::G1)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsLongBranch.cpp | 235 MIB.addReg(MO.getReg());
289 .addReg(Mips::SP).addImm(-8);
290 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
291 .addReg(Mips::SP).addImm(0);
300 .addReg(Mips::AT).addImm(Lo);
302 .addReg(Mips::RA).addReg(Mips::AT);
304 .addReg(Mips::SP).addImm(0);
307 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
309 .addReg(Mips::SP).addImm(8))
[all...] |
| Mips16InstrInfo.cpp | 94 MIB.addReg(DestReg, RegState::Define);
97 MIB.addReg(SrcReg, getKillRegState(KillSrc));
112 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
201 MIB1.addReg(Mips::SP);
205 MIB2.addReg(Mips::SP);
209 MIB3.addReg(Mips::SP);
241 MIB1.addReg(Mips::SP);
245 MIB0.addReg(Mips::A0);
248 MIB2.addReg(Mips::SP);
252 MIB3.addReg(Mips::SP)
[all...] |
| MipsSEInstrInfo.cpp | 114 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
134 .addReg(DestReg, RegState::ImplicitDefine);
168 MIB.addReg(DestReg, RegState::Define);
171 MIB.addReg(SrcReg, getKillRegState(KillSrc));
174 MIB.addReg(ZeroReg);
208 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
323 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
326 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill)
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 32 MCInstBuilder &addReg(unsigned Reg) {
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 49 .addReg(SrcReg, getKillRegState(KillSrc));
56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
|
| R600InstrInfo.cpp | 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex))
62 .addReg(0) // PREDICATE_BIT
63 .addReg(DestReg, RegState::Define | RegState::Implicit);
72 .addReg(SrcReg, getKillRegState(KillSrc))
74 .addReg(0); // PREDICATE_BIT
82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT
271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0)
[all...] |
| R600ISelLowering.cpp | 69 .addReg(AMDGPU::PRED_SEL_OFF);
80 .addReg(AMDGPU::PRED_SEL_OFF);
92 .addReg(AMDGPU::PRED_SEL_OFF);
103 .addReg(ConstantReg);
131 .addReg(AMDGPU::ALU_LITERAL_X)
132 .addReg(AMDGPU::PRED_SEL_OFF)
136 .addReg(ShiftValue)
137 .addReg(AMDGPU::PRED_SEL_OFF);
140 .addReg(NewAddr)
173 .addReg(t0, RegState::Implicit
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 48 NVPTX::VRFrame).addReg(LocalReg);
55 NVPTX::VRFrame).addReg(LocalReg);
|
| NVPTXInstrInfo.cpp | 44 .addReg(SrcReg, getKillRegState(KillSrc));
47 .addReg(SrcReg, getKillRegState(KillSrc));
50 .addReg(SrcReg, getKillRegState(KillSrc));
53 .addReg(SrcReg, getKillRegState(KillSrc));
56 .addReg(SrcReg, getKillRegState(KillSrc));
59 .addReg(SrcReg, getKillRegState(KillSrc));
261 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
267 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIInstrInfo.cpp | 49 .addReg(SrcReg, getKillRegState(KillSrc));
56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
|
| R600InstrInfo.cpp | 59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define)
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex))
62 .addReg(0) // PREDICATE_BIT
63 .addReg(DestReg, RegState::Define | RegState::Implicit);
72 .addReg(SrcReg, getKillRegState(KillSrc))
74 .addReg(0); // PREDICATE_BIT
82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X);
85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT
271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0)
[all...] |
| R600ISelLowering.cpp | 69 .addReg(AMDGPU::PRED_SEL_OFF);
80 .addReg(AMDGPU::PRED_SEL_OFF);
92 .addReg(AMDGPU::PRED_SEL_OFF);
103 .addReg(ConstantReg);
131 .addReg(AMDGPU::ALU_LITERAL_X)
132 .addReg(AMDGPU::PRED_SEL_OFF)
136 .addReg(ShiftValue)
137 .addReg(AMDGPU::PRED_SEL_OFF);
140 .addReg(NewAddr)
173 .addReg(t0, RegState::Implicit
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill);
71 .addReg(MSP430::SPW);
99 .addReg(MSP430::SPW).addImm(NumBytes);
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
162 .addReg(MSP430::SPW).addImm(CSSize);
171 .addReg(MSP430::SPW).addImm(NumBytes);
200 .addReg(Reg, RegState::Kill);
249 .addReg(MSP430::SPW).addImm(Amount);
258 .addReg(MSP430::SPW).addImm(Amount);
276 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt)
[all...] |
