| /bionic/libc/kernel/arch-mips/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.d (…)
[all...] |
| processor.h | 47 dspreg_t dspr[NUM_DSP_REGS]; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.d (…)
[all...] |
| processor.h | 47 dspreg_t dspr[NUM_DSP_REGS]; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /external/kernel-headers/original/asm-mips/ |
| dsp.h | 45 tsk->thread.dsp.dspr[0] = mfhi1(); \
46 tsk->thread.dsp.dspr[1] = mflo1(); \
47 tsk->thread.dsp.dspr[2] = mfhi2(); \
48 tsk->thread.dsp.dspr[3] = mflo2(); \
49 tsk->thread.dsp.dspr[4] = mfhi3(); \
50 tsk->thread.dsp.dspr[5] = mflo3(); \
62 mthi1(tsk->thread.dsp.dspr[0]); \
63 mtlo1(tsk->thread.dsp.dspr[1]); \
64 mthi2(tsk->thread.dsp.dspr[2]); \
65 mtlo2(tsk->thread.dsp.dspr[3]);
[all...] |
| processor.h | 100 dspreg_t dspr[NUM_DSP_REGS]; member in struct:mips_dsp_state
192 .dspr = {0, }, \
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.d (…)
[all...] |
| processor.h | 47 dspreg_t dspr[NUM_DSP_REGS]; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.d (…)
[all...] |
| processor.h | 47 dspreg_t dspr[NUM_DSP_REGS]; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/9/platforms/android-14/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.d (…)
[all...] |
| processor.h | 47 dspreg_t dspr[NUM_DSP_REGS]; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/9/platforms/android-18/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.d (…)
[all...] |
| processor.h | 47 dspreg_t dspr[NUM_DSP_REGS]; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /prebuilts/ndk/9/platforms/android-9/arch-mips/usr/include/asm/ |
| dsp.h | 30 #define __save_dsp(tsk) do { tsk->thread.dsp.dspr[0] = mfhi1(); tsk->thread.dsp.dspr[1] = mflo1(); tsk->thread.dsp.dspr[2] = mfhi2(); tsk->thread.dsp.dspr[3] = mflo2(); tsk->thread.dsp.dspr[4] = mfhi3(); tsk->thread.dsp.dspr[5] = mflo3(); tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK); } while (0)
32 #define __restore_dsp(tsk) do { mthi1(tsk->thread.dsp.dspr[0]); mtlo1(tsk->thread.dsp.dspr[1]); mthi2(tsk->thread.dsp.dspr[2]); mtlo2(tsk->thread.dsp.dspr[3]); mthi3(tsk->thread.dsp.dspr[4]); mtlo3(tsk->thread.dsp.dspr[5]); wrdsp(tsk->thread.dsp.d (…)
[all...] |
| processor.h | 47 dspreg_t dspr[NUM_DSP_REGS]; member in struct:mips_dsp_state
79 #define INIT_THREAD { .reg16 = 0, .reg17 = 0, .reg18 = 0, .reg19 = 0, .reg20 = 0, .reg21 = 0, .reg22 = 0, .reg23 = 0, .reg29 = 0, .reg30 = 0, .reg31 = 0, .cp0_status = 0, .fpu = { .fpr = {0,}, .fcr31 = 0, }, FPAFF_INIT .dsp = { .dspr = {0, }, .dspcontrol = 0, }, .cp0_badvaddr = 0, .cp0_baduaddr = 0, .error_code = 0, .trap_no = 0, .irix_trampoline = 0, .irix_oldctx = 0, }
|
| /external/eigen/Eigen/src/misc/ |
| blas.h | 301 int BLASFUNC(dspr) (char *, int *, double *, double *, int *,
[all...] |
| /external/eigen/bench/btl/libs/BLAS/ |
| blas.h | 322 int BLASFUNC(dspr) (char *, int *, double *, double *, int *,
[all...] |
