/packages/apps/Gallery2/jni/filters/ |
fx.c | 23 float fr10 = (src[p+off[4]])*(1-dr)+(src[p+off[5]])*dr; local 26 float frb1 = fr10 * (1-db)+fr11*db;
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/art/compiler/dex/quick/arm/ |
arm_lir.h | 174 fr10 = 10 + ARM_FP_REG_OFFSET, enumerator in enum:art::ArmNativeRegisterPool 201 dr5 = fr10 + ARM_FP_DOUBLE,
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target_arm.cc | 30 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15, 35 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15}; 666 Clobber(fr10);
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/external/libffi/src/sh/ |
sysv.S | 151 fmov.s @r15+,fr10 162 fmov.s @r15+,fr10 204 fmov.s @r15+,fr10 219 fmov.s @r15+,fr10 536 fmov.s fr10,@-r1 546 fmov.s fr10,@-r1
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/art/compiler/dex/quick/x86/ |
target_x86.cc | 38 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15 44 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15
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x86_lir.h | 190 fr10 = 10 + X86_FP_REG_OFFSET, enumerator in enum:art::X86NativeRegisterPool
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/dalvik/vm/compiler/codegen/arm/ |
ArmLIR.h | 243 fr10 = 10 + FP_REG_OFFSET, enumerator in enum:NativeRegisterPool 270 dr5 = fr10 + FP_DOUBLE, [all...] |
/dalvik/vm/compiler/template/mips/ |
TEMPLATE_RESTORE_STATE.S | 66 lw f10, fr10*4(a0) # restore f10
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TEMPLATE_SAVE_STATE.S | 78 sw f10, fr10*4(a0) # save f10
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TEMPLATE_MEM_OP_DECODE.S | 22 sw f10, fr10*-4(sp) # push f10 140 lw f10, fr10*-4(sp) # pop f10
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/external/chromium_org/third_party/openssl/openssl/crypto/ |
pariscid.pl | 68 fcpy,dbl %fr0,%fr10
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/external/openssl/crypto/ |
pariscid.pl | 68 fcpy,dbl %fr0,%fr10
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/dalvik/vm/compiler/template/out/ |
CompilerTemplateAsm-mips.S | [all...] |
/external/libffi/src/sh64/ |
sysv.S | 194 fld.s r15, OFS_FLT, fr10
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/external/chromium_org/third_party/openssl/openssl/crypto/bn/asm/ |
pa-risc2.s | 877 XMPYU %fr8L,%fr7L,%fr10 ;offset 0xa80 878 FSTD %fr10,-136(%r30) ;offset 0xa84 991 b4 .reg %fr10 [all...] |
pa-risc2W.s | 816 XMPYU %fr8L,%fr7L,%fr10 817 FSTD %fr10,-256(%r30) 978 b4 .reg %fr10 [all...] |
/external/openssl/crypto/bn/asm/ |
pa-risc2.s | 877 XMPYU %fr8L,%fr7L,%fr10 ;offset 0xa80 878 FSTD %fr10,-136(%r30) ;offset 0xa84 991 b4 .reg %fr10 [all...] |
pa-risc2W.s | 816 XMPYU %fr8L,%fr7L,%fr10 817 FSTD %fr10,-256(%r30) 978 b4 .reg %fr10 [all...] |