| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 43 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
56 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
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| Mips16FrameLowering.cpp | 171 MF.getRegInfo().setPhysRegUsed(Mips::RA);
172 MF.getRegInfo().setPhysRegUsed(Mips::S0);
173 MF.getRegInfo().setPhysRegUsed(Mips::S1);
174 MF.getRegInfo().setPhysRegUsed(Mips::S2);
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| MipsSEISelDAGToDAG.cpp | 115 MachineRegisterInfo &RegInfo = MF.getRegInfo();
130 MF.getRegInfo().addLiveIn(Mips::T9_64);
158 MF.getRegInfo().addLiveIn(Mips::T9);
193 MF.getRegInfo().addLiveIn(Mips::V0);
202 MachineRegisterInfo *MRI = &MF.getRegInfo();
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| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 35 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
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| PHIEliminationUtils.cpp | 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo();
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| VirtRegMap.cpp | 53 MRI = &mf.getRegInfo();
67 unsigned NumRegs = MF->getRegInfo().getNumVirtRegs();
102 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
206 MRI = &MF->getRegInfo();
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| RegAllocBase.cpp | 57 MRI = &vrm.getRegInfo();
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| CalcSpillWeights.cpp | 49 MachineRegisterInfo &MRI = MF.getRegInfo();
115 MachineRegisterInfo &mri = MF.getRegInfo();
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| DeadMachineInstructionElim.cpp | 88 MRI = &MF.getRegInfo();
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| LiveRegMatrix.cpp | 51 MRI = &MF.getRegInfo();
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| OptimizePHIs.cpp | 64 MRI = &Fn.getRegInfo();
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| ProcessImplicitDefs.cpp | 146 MRI = &MF.getRegInfo();
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| /dalvik/vm/compiler/codegen/ |
| RallocUtil.cpp | 83 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg)
107 RegisterInfo *info1 = getRegInfo(cUnit, reg1);
108 RegisterInfo *info2 = getRegInfo(cUnit, reg2);
126 RegisterInfo *info = getRegInfo(cUnit, reg);
439 RegisterInfo *p = getRegInfo(cUnit, reg);
469 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
485 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
496 RegisterInfo *infoLo = getRegInfo(cUnit, rl.lowReg);
497 RegisterInfo *infoHi = getRegInfo(cUnit, rl.highReg);
527 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 40 MachineRegisterInfo &MRI = MF.getRegInfo();
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| /dalvik/vm/compiler/codegen/mips/ |
| RallocUtil.cpp | 85 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg)
109 RegisterInfo *info1 = getRegInfo(cUnit, reg1);
110 RegisterInfo *info2 = getRegInfo(cUnit, reg2);
128 RegisterInfo *info = getRegInfo(cUnit, reg);
505 RegisterInfo *p = getRegInfo(cUnit, reg);
535 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
551 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg);
562 RegisterInfo *infoLo = getRegInfo(cUnit, rl.lowReg);
563 RegisterInfo *infoHi = getRegInfo(cUnit, rl.highReg);
599 RegisterInfo *p = getRegInfo(cUnit, rl.lowReg)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 283 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
307 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
315 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC);
332 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
340 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC);
382 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
394 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
426 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
438 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
465 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC)
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIFixSGPRCopies.cpp | 132 MachineRegisterInfo &MRI = MF.getRegInfo();
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| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 90 MachineRegisterInfo &MRI = MF.getRegInfo();
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| AMDGPUInstrInfo.cpp | 241 MachineRegisterInfo &MRI = MF.getRegInfo();
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| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 117 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
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| VirtRegMap.h | 85 MachineRegisterInfo &getRegInfo() const { return *MRI; }
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 90 MachineRegisterInfo &MRI = MF.getRegInfo();
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| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 164 MachineRegisterInfo &MRI = MF.getRegInfo();
175 MachineRegisterInfo &MRI = MF.getRegInfo();
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| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 363 MF.getRegInfo().setPhysRegUsed(AArch64::X29);
364 MF.getRegInfo().setPhysRegUsed(AArch64::X30);
386 !MF.getRegInfo().isPhysRegUsed(CSRegs[i])) {
393 MF.getRegInfo().setPhysRegUsed(ExtraReg);
413 && MBB.getParent()->getRegInfo().isLiveIn(Reg))
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| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 201 const MachineRegisterInfo &MRI = MF.getRegInfo();
248 MachineRegisterInfo *MRI = &MF.getRegInfo();
320 const MachineRegisterInfo *MRI = &MF.getRegInfo();
575 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
749 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
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