| /external/llvm/lib/CodeGen/ |
| ScheduleDAG.cpp | 71 if (!Required && I->getSUnit() == D.getSUnit())
76 SUnit *PredSU = I->getSUnit();
95 SUnit *N = D.getSUnit();
141 SUnit *N = D.getSUnit();
187 SUnit *SuccSU = I->getSUnit();
203 SUnit *PredSU = I->getSUnit();
244 SUnit *PredSU = I->getSUnit();
277 SUnit *SuccSU = I->getSUnit();
303 unsigned MaxDepth = BestI->getSUnit()->getDepth()
[all...] |
| LatencyPriorityQueue.cpp | 59 SUnit &Pred = *I->getSUnit();
78 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
94 AdjustPriorityOfUnscheduledPreds(I->getSUnit());
|
| ScheduleDAGInstrs.cpp | 418 SUnit *DefSU = getSUnit(Def);
592 iterateChainSucc (AA, MFI, SUa, I->getSUnit(), ExitSU, Depth, Visited);
623 iterateChainSucc (AA, MFI, SU, J->getSUnit(),
[all...] |
| MachineScheduler.cpp | 335 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU))
337 Topo.AddPred(SuccSU, PredDep.getSUnit());
349 SUnit *SuccSU = SuccEdge->getSUnit();
383 SUnit *PredSU = PredEdge->getSUnit();
763 if (SUnit *SU = getSUnit(&(*MI)))
843 if (SI->getSUnit() == SUb)
845 DEBUG(dbgs() << " Copy Succ SU(" << SI->getSUnit()->NodeNum << ")\n");
846 DAG->addEdge(SI->getSUnit(), SDep(SUb, SDep::Artificial));
869 ChainPredID = PI->getSUnit()->NodeNum;
[all...] |
| AggressiveAntiDepBreaker.cpp | 282 const SUnit *PredSU = P->getSUnit();
295 return (Next) ? Next->getSUnit() : 0;
795 SUnit *NextSU = Edge->getSUnit();
840 if (P->getSUnit() == NextSU ?
849 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
854 } else if ((P->getSUnit() != NextSU) &&
[all...] |
| CriticalAntiDepBreaker.cpp | 132 const SUnit *PredSU = P->getSUnit();
518 const SUnit *NextSU = Edge->getSUnit();
542 if (P->getSUnit() == NextSU ?
|
| PostRASchedulerList.cpp | 564 SUnit *SuccSU = SuccEdge->getSUnit();
|
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 175 /// getSUnit - Return an existing SUnit for this MI, or NULL.
176 SUnit *getSUnit(MachineInstr *MI) const;
245 /// getSUnit - Return an existing SUnit for this MI, or NULL.
246 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const {
|
| ScheduleDAG.h | 159 //// getSUnit - Return the SUnit to which this edge points.
160 SUnit *getSUnit() const {
440 if (Preds[i].getSUnit() == N)
448 if (Succs[i].getSUnit() == N)
618 return Node->Preds[Operand].getSUnit();
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 78 SUnit *PredSU = I->getSUnit();
116 SUnit *SuccSU = I->getSUnit();
220 SUnit &Pred = *I->getSUnit();
238 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
282 if (I->getSUnit() == SU)
513 if (I->isCtrl() || (I->getSUnit()->NumRegDefsLeft == 0))
515 --I->getSUnit()->NumRegDefsLeft;
529 adjustPriorityOfUnscheduledPreds(I->getSUnit());
|
| ScheduleDAGFast.cpp | 140 SUnit *PredSU = PredEdge->getSUnit();
172 LiveRegDefs[I->getReg()] = I->getSUnit();
196 if (LiveRegCycles[I->getReg()] == I->getSUnit()->getHeight()) {
289 else if (I->getSUnit()->getNode() &&
290 I->getSUnit()->getNode()->isOperandOf(LoadNode))
303 if (ChainPred.getSUnit()) {
322 SUnit *SuccDep = D.getSUnit();
330 SUnit *SuccDep = D.getSUnit();
369 SUnit *SuccSU = I->getSUnit();
406 SUnit *SuccSU = I->getSUnit();
[all...] |
| ScheduleDAGRRList.cpp | 199 Topo.AddPred(SU, D.getSUnit());
207 Topo.RemovePred(SU, D.getSUnit());
365 SUnit *PredSU = PredEdge->getSUnit();
535 assert((!RegDef || RegDef == SU || RegDef == I->getSUnit()) &&
537 LiveRegDefs[I->getReg()] = I->getSUnit();
791 SUnit *PredSU = PredEdge->getSUnit();
813 assert(LiveRegDefs[I->getReg()] == I->getSUnit() &&
859 I->getSUnit()->getHeight() < LiveRegGens[I->getReg()]->getHeight())
860 LiveRegGens[I->getReg()] = I->getSUnit();
[all...] |
| ScheduleDAGVLIW.cpp | 116 SUnit *SuccSU = D.getSUnit();
|
| ScheduleDAGSDNodes.cpp | 763 if (I->getSUnit()->CopyDstRC) {
765 DenseMap<SUnit*, unsigned>::iterator VRI = VRBaseMap.find(I->getSUnit());
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 75 if (I->getSUnit() == SU)
226 unsigned PredReadyCycle = I->getSUnit()->TopReadyCycle;
245 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle;
427 SUnit &Pred = *I->getSUnit();
445 SUnit &Succ = *I->getSUnit();
508 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
514 if (getSingleUnscheduledSucc(I->getSUnit()) == SU)
|
| HexagonVLIWPacketizer.cpp | 827 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600Packetizer.cpp | 187 if (Dep.getSUnit() != SUI)
|
