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  /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/test/
test_tcl.py 12 from Tkinter import Tcl
26 self.interp = Tcl()
29 tcl = self.interp
30 tcl.eval('set a 1')
31 self.assertEqual(tcl.eval('set a'),'1')
34 tcl = self.interp
35 self.assertRaises(TclError,tcl.eval,'set a')
38 tcl = self.interp
39 self.assertRaises(TclError,tcl.eval,'this is wrong')
42 tcl = self.inter
    [all...]
  /prebuilts/python/linux-x86/2.7.5/lib/python2.7/test/
test_tcl.py 12 from Tkinter import Tcl
26 self.interp = Tcl()
29 tcl = self.interp
30 tcl.eval('set a 1')
31 self.assertEqual(tcl.eval('set a'),'1')
34 tcl = self.interp
35 self.assertRaises(TclError,tcl.eval,'set a')
38 tcl = self.interp
39 self.assertRaises(TclError,tcl.eval,'this is wrong')
42 tcl = self.inter
    [all...]
  /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/lib-tk/test/test_tkinter/
test_loadtk.py 5 from Tkinter import Tcl, TclError
13 tcl = Tcl()
14 self.assertRaises(TclError,tcl.winfo_geometry)
15 tcl.loadtk()
16 self.assertEqual('1x1+0+0', tcl.winfo_geometry())
17 tcl.destroy()
38 tcl = Tcl()
39 self.assertRaises(TclError, tcl.winfo_geometry
    [all...]
  /prebuilts/python/linux-x86/2.7.5/lib/python2.7/lib-tk/test/test_tkinter/
test_loadtk.py 5 from Tkinter import Tcl, TclError
13 tcl = Tcl()
14 self.assertRaises(TclError,tcl.winfo_geometry)
15 tcl.loadtk()
16 self.assertEqual('1x1+0+0', tcl.winfo_geometry())
17 tcl.destroy()
38 tcl = Tcl()
39 self.assertRaises(TclError, tcl.winfo_geometry
    [all...]
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/r200/
r200_cmdbuf.c 75 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl );
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
154 rmesa->radeon.tcl.elt_dma_bo,
163 int nr, elt_used = rmesa->tcl.elt_used;
165 radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used);
172 radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
174 r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
176 radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
177 rmesa->radeon.tcl.elt_dma_bo = NULL;
196 radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo
    [all...]
r200_maos_arrays.c 117 if (!rmesa->radeon.tcl.aos[i].bo) {
120 &(rmesa->radeon.tcl.aos[nr]),
127 &(rmesa->radeon.tcl.aos[nr]),
176 if (!rmesa->radeon.tcl.aos[nr].bo) {
178 &(rmesa->radeon.tcl.aos[nr]),
197 rmesa->radeon.tcl.aos_count = nr;
r200_state.c 390 R200_STATECHANGE(rmesa, tcl);
391 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK;
394 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_LINEAR;
405 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP;
410 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP2;
496 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
523 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
524 R200_STATECHANGE(rmesa, tcl );
525 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
537 R200_STATECHANGE( rmesa, tcl );
    [all...]
r200_tcl.c 145 rmesa->tcl.elt_used + nr*2 < R200_ELT_BUF_SZ) {
147 GLushort *dest = (GLushort *)(rmesa->radeon.tcl.elt_dma_bo->ptr +
148 rmesa->radeon.tcl.elt_dma_offset + rmesa->tcl.elt_used);
150 rmesa->tcl.elt_used += nr*2;
159 rmesa->radeon.tcl.aos_count, 0 );
161 r200EmitMaxVtxIndex(rmesa, rmesa->radeon.tcl.aos[0].count);
162 return r200AllocEltsOpenEnded( rmesa, rmesa->tcl.hw_primitive, nr );
187 // fprintf(stderr,"Emit prim %d\n", rmesa->radeon.tcl.aos_count);
190 rmesa->radeon.tcl.aos_count
    [all...]
  /external/mesa3d/src/mesa/drivers/dri/r200/
r200_cmdbuf.c 75 insert_at_tail_if( &rmesa->radeon.hw.atomlist, &rmesa->hw.tcl );
151 OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
154 rmesa->radeon.tcl.elt_dma_bo,
163 int nr, elt_used = rmesa->tcl.elt_used;
165 radeon_print(RADEON_RENDER, RADEON_VERBOSE, "%s %x %d\n", __FUNCTION__, rmesa->tcl.hw_primitive, elt_used);
172 radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
174 r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
176 radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
177 rmesa->radeon.tcl.elt_dma_bo = NULL;
196 radeonAllocDmaRegion(&rmesa->radeon, &rmesa->radeon.tcl.elt_dma_bo
    [all...]
r200_maos_arrays.c 117 if (!rmesa->radeon.tcl.aos[i].bo) {
120 &(rmesa->radeon.tcl.aos[nr]),
127 &(rmesa->radeon.tcl.aos[nr]),
176 if (!rmesa->radeon.tcl.aos[nr].bo) {
178 &(rmesa->radeon.tcl.aos[nr]),
197 rmesa->radeon.tcl.aos_count = nr;
r200_state.c 390 R200_STATECHANGE(rmesa, tcl);
391 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~R200_TCL_FOG_MASK;
394 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_LINEAR;
405 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP;
410 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= R200_TCL_FOG_EXP2;
496 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
523 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
524 R200_STATECHANGE(rmesa, tcl );
525 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
537 R200_STATECHANGE( rmesa, tcl );
    [all...]
  /external/chromium_org/third_party/mesa/src/src/mesa/drivers/dri/radeon/
radeon_ioctl.c 77 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl);
174 uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
183 nr = rmesa->tcl.elt_used;
233 rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw;
260 rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw;
261 rmesa->tcl.elt_used = min_nr;
263 retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
308 rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
310 (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4)
    [all...]
radeon_maos_arrays.c 159 if (!rmesa->tcl.obj.buf)
161 &(rmesa->tcl.aos[nr]),
179 if (!rmesa->tcl.norm.buf)
181 &(rmesa->tcl.aos[nr]),
205 if (!rmesa->tcl.rgba.buf)
207 &(rmesa->tcl.aos[nr]),
218 if (!rmesa->tcl.spec.buf) {
221 &(rmesa->tcl.aos[nr]),
236 if (!rmesa->tcl.fog.buf)
238 &(rmesa->tcl.aos[nr])
    [all...]
radeon_maos_verts.c 316 GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
366 if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) {
367 RADEON_STATECHANGE( rmesa, tcl );
368 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
375 if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
376 rmesa->radeon.tcl.aos[0].bo)
379 if (rmesa->radeon.tcl.aos[0].bo)
383 &rmesa->radeon.tcl.aos[0].bo,
384 &rmesa->radeon.tcl.aos[0].offset,
396 _math_trans_4f( rmesa->tcl.ObjClean.data
    [all...]
radeon_tcl.c 114 #define GET_MESA_ELTS() rmesa->tcl.Elts
153 rmesa->radeon.tcl.aos_count, 0 );
155 return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
156 rmesa->tcl.hw_primitive, nr );
177 rmesa->radeon.tcl.aos_count,
183 rmesa->tcl.vertex_format,
184 rmesa->tcl.hw_primitive,
202 rmesa->tcl.hw_primitive == (PRIM| \
259 if (newprim != rmesa->tcl.hw_primitive ||
262 rmesa->tcl.hw_primitive = newprim
    [all...]
radeon_state.c 325 RADEON_STATECHANGE(rmesa, tcl);
326 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
329 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR;
332 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP;
335 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2;
404 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
431 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
432 RADEON_STATECHANGE(rmesa, tcl );
433 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
445 RADEON_STATECHANGE( rmesa, tcl );
    [all...]
  /external/chromium_org/third_party/sqlite/src/test/
lock_common.tcl 22 proc code2 {tcl} { testfixture $::code2_chan $tcl }
23 proc code3 {tcl} { testfixture $::code3_chan $tcl }
26 proc code2 {tcl} { uplevel #0 $tcl }
27 proc code3 {tcl} { uplevel #0 $tcl }
32 proc code1 {tcl} { uplevel #0 $tcl }
    [all...]
fuzz_malloc.test 18 source $testdir/tester.tcl
25 source $testdir/malloc_common.tcl
26 source $testdir/fuzz_common.tcl
mallocAll.test 30 source $testdir/tester.tcl
tkt2391.test 15 source $testdir/tester.tcl
  /external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_ioctl.c 77 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl);
174 uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
183 nr = rmesa->tcl.elt_used;
233 rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw;
260 rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw;
261 rmesa->tcl.elt_used = min_nr;
263 retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
308 rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
310 (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4)
    [all...]
radeon_maos_arrays.c 159 if (!rmesa->tcl.obj.buf)
161 &(rmesa->tcl.aos[nr]),
179 if (!rmesa->tcl.norm.buf)
181 &(rmesa->tcl.aos[nr]),
205 if (!rmesa->tcl.rgba.buf)
207 &(rmesa->tcl.aos[nr]),
218 if (!rmesa->tcl.spec.buf) {
221 &(rmesa->tcl.aos[nr]),
236 if (!rmesa->tcl.fog.buf)
238 &(rmesa->tcl.aos[nr])
    [all...]
radeon_maos_verts.c 316 GLuint vtx = (rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] &
366 if (vtx != rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT]) {
367 RADEON_STATECHANGE( rmesa, tcl );
368 rmesa->hw.tcl.cmd[TCL_OUTPUT_VTXFMT] = vtx;
375 if (rmesa->tcl.vertex_format == setup_tab[i].vertex_format &&
376 rmesa->radeon.tcl.aos[0].bo)
379 if (rmesa->radeon.tcl.aos[0].bo)
383 &rmesa->radeon.tcl.aos[0].bo,
384 &rmesa->radeon.tcl.aos[0].offset,
396 _math_trans_4f( rmesa->tcl.ObjClean.data
    [all...]
radeon_tcl.c 114 #define GET_MESA_ELTS() rmesa->tcl.Elts
153 rmesa->radeon.tcl.aos_count, 0 );
155 return radeonAllocEltsOpenEnded( rmesa, rmesa->tcl.vertex_format,
156 rmesa->tcl.hw_primitive, nr );
177 rmesa->radeon.tcl.aos_count,
183 rmesa->tcl.vertex_format,
184 rmesa->tcl.hw_primitive,
202 rmesa->tcl.hw_primitive == (PRIM| \
259 if (newprim != rmesa->tcl.hw_primitive ||
262 rmesa->tcl.hw_primitive = newprim
    [all...]
radeon_state.c 325 RADEON_STATECHANGE(rmesa, tcl);
326 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] &= ~RADEON_TCL_FOG_MASK;
329 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_LINEAR;
332 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP;
335 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] |= RADEON_TCL_FOG_EXP2;
404 GLuint t = rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL];
431 if ( rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] != t ) {
432 RADEON_STATECHANGE(rmesa, tcl );
433 rmesa->hw.tcl.cmd[TCL_UCP_VERT_BLEND_CTL] = t;
445 RADEON_STATECHANGE( rmesa, tcl );
    [all...]

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