/dalvik/vm/mterp/armv5te/ |
OP_AND_INT_LIT8.S | 2 %include "armv5te/binopLit8.S" {"instr":"and r0, r0, r1"}
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OP_DIV_DOUBLE.S | 2 %include "armv5te/binopWide.S" {"instr":"bl __aeabi_ddiv"}
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OP_DIV_DOUBLE_2ADDR.S | 2 %include "armv5te/binopWide2addr.S" {"instr":"bl __aeabi_ddiv"}
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OP_DIV_FLOAT.S | 2 %include "armv5te/binop.S" {"instr":"bl __aeabi_fdiv"}
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OP_DIV_FLOAT_2ADDR.S | 2 %include "armv5te/binop2addr.S" {"instr":"bl __aeabi_fdiv"}
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OP_DIV_INT.S | 2 %include "armv5te/binop.S" {"instr":"bl __aeabi_idiv","chkzero":"1"}
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OP_DIV_INT_2ADDR.S | 2 %include "armv5te/binop2addr.S" {"instr":"bl __aeabi_idiv","chkzero":"1"}
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OP_DIV_INT_LIT16.S | 2 %include "armv5te/binopLit16.S" {"instr":"bl __aeabi_idiv","chkzero":"1"}
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OP_DIV_INT_LIT8.S | 2 %include "armv5te/binopLit8.S" {"instr":"bl __aeabi_idiv","chkzero":"1"}
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OP_DIV_LONG.S | 2 %include "armv5te/binopWide.S" {"instr":"bl __aeabi_ldivmod", "chkzero":"1"}
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OP_DIV_LONG_2ADDR.S | 2 %include "armv5te/binopWide2addr.S" {"instr":"bl __aeabi_ldivmod", "chkzero":"1"}
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OP_DOUBLE_TO_FLOAT.S | 2 %include "armv5te/unopNarrower.S" {"instr":"bl __aeabi_d2f"}
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OP_FLOAT_TO_DOUBLE.S | 2 %include "armv5te/unopWider.S" {"instr":"bl __aeabi_f2d"}
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OP_INT_TO_DOUBLE.S | 2 %include "armv5te/unopWider.S" {"instr":"bl __aeabi_i2d"}
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OP_INT_TO_FLOAT.S | 2 %include "armv5te/unop.S" {"instr":"bl __aeabi_i2f"}
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OP_INT_TO_LONG.S | 2 %include "armv5te/unopWider.S" {"instr":"mov r1, r0, asr #31"}
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OP_LONG_TO_DOUBLE.S | 2 %include "armv5te/unopWide.S" {"instr":"bl __aeabi_l2d"}
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OP_LONG_TO_FLOAT.S | 2 %include "armv5te/unopNarrower.S" {"instr":"bl __aeabi_l2f"}
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OP_MUL_DOUBLE.S | 2 %include "armv5te/binopWide.S" {"instr":"bl __aeabi_dmul"}
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OP_MUL_DOUBLE_2ADDR.S | 2 %include "armv5te/binopWide2addr.S" {"instr":"bl __aeabi_dmul"}
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OP_MUL_FLOAT.S | 2 %include "armv5te/binop.S" {"instr":"bl __aeabi_fmul"}
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OP_MUL_FLOAT_2ADDR.S | 2 %include "armv5te/binop2addr.S" {"instr":"bl __aeabi_fmul"}
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OP_NEG_DOUBLE.S | 2 %include "armv5te/unopWide.S" {"instr":"add r1, r1, #0x80000000"}
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OP_NEG_FLOAT.S | 2 %include "armv5te/unop.S" {"instr":"add r0, r0, #0x80000000"}
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OP_NEG_INT.S | 2 %include "armv5te/unop.S" {"instr":"rsb r0, r0, #0"}
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