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  /dalvik/vm/compiler/template/mips/
TEMPLATE_SUB_FLOAT_VFP.S 2 %include "mips/fbinop.S" {"instr":"JAL(__subsf3)","instr_f":"sub.s fv0, fa0, fa1"}
  /dalvik/vm/mterp/armv5te/
OP_ADD_LONG.S 2 %include "armv5te/binopWide.S" {"preinstr":"adds r0, r0, r2", "instr":"adc r1, r1, r3"}
OP_ADD_LONG_2ADDR.S 2 %include "armv5te/binopWide2addr.S" {"preinstr":"adds r0, r0, r2", "instr":"adc r1, r1, r3"}
OP_AND_LONG.S 2 %include "armv5te/binopWide.S" {"preinstr":"and r0, r0, r2", "instr":"and r1, r1, r3"}
OP_AND_LONG_2ADDR.S 2 %include "armv5te/binopWide2addr.S" {"preinstr":"and r0, r0, r2", "instr":"and r1, r1, r3"}
OP_INT_TO_BYTE.S 2 %include "armv5te/unop.S" {"preinstr":"mov r0, r0, asl #24", "instr":"mov r0, r0, asr #24"}
OP_INT_TO_CHAR.S 2 %include "armv5te/unop.S" {"preinstr":"mov r0, r0, asl #16", "instr":"mov r0, r0, lsr #16"}
OP_INT_TO_SHORT.S 2 %include "armv5te/unop.S" {"preinstr":"mov r0, r0, asl #16", "instr":"mov r0, r0, asr #16"}
OP_MUL_INT.S 3 %include "armv5te/binop.S" {"instr":"mul r0, r1, r0"}
OP_MUL_INT_2ADDR.S 3 %include "armv5te/binop2addr.S" {"instr":"mul r0, r1, r0"}
OP_MUL_INT_LIT16.S 3 %include "armv5te/binopLit16.S" {"instr":"mul r0, r1, r0"}
OP_MUL_INT_LIT8.S 3 %include "armv5te/binopLit8.S" {"instr":"mul r0, r1, r0"}
OP_NEG_LONG.S 2 %include "armv5te/unopWide.S" {"preinstr":"rsbs r0, r0, #0", "instr":"rsc r1, r1, #0"}
OP_OR_LONG.S 2 %include "armv5te/binopWide.S" {"preinstr":"orr r0, r0, r2", "instr":"orr r1, r1, r3"}
OP_OR_LONG_2ADDR.S 2 %include "armv5te/binopWide2addr.S" {"preinstr":"orr r0, r0, r2", "instr":"orr r1, r1, r3"}
OP_REM_DOUBLE.S 3 %include "armv5te/binopWide.S" {"instr":"bl fmod"}
OP_REM_DOUBLE_2ADDR.S 3 %include "armv5te/binopWide2addr.S" {"instr":"bl fmod"}
OP_REM_FLOAT.S 3 %include "armv5te/binop.S" {"instr":"bl fmodf"}
OP_REM_FLOAT_2ADDR.S 3 %include "armv5te/binop2addr.S" {"instr":"bl fmodf"}
OP_REM_INT.S 3 %include "armv5te/binop.S" {"instr":"bl __aeabi_idivmod", "result":"r1", "chkzero":"1"}
OP_REM_INT_2ADDR.S 3 %include "armv5te/binop2addr.S" {"instr":"bl __aeabi_idivmod", "result":"r1", "chkzero":"1"}
OP_REM_INT_LIT16.S 3 %include "armv5te/binopLit16.S" {"instr":"bl __aeabi_idivmod", "result":"r1", "chkzero":"1"}
OP_REM_INT_LIT8.S 3 %include "armv5te/binopLit8.S" {"instr":"bl __aeabi_idivmod", "result":"r1", "chkzero":"1"}
OP_SHL_INT.S 2 %include "armv5te/binop.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asl r1"}
OP_SHL_INT_2ADDR.S 2 %include "armv5te/binop2addr.S" {"preinstr":"and r1, r1, #31", "instr":"mov r0, r0, asl r1"}

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