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  /external/llvm/test/CodeGen/R600/
llvm.AMDGPU.umin.ll 1 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
llvm.SI.tid.ll 1 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
load64.ll 1 ; RUN: llc < %s -march=r600 -mcpu=tahiti | FileCheck %s
lshl.ll 1 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
lshr.ll 1 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
mulhu.ll 1 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
selectcc-icmp-select-float.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
seto.ll 1 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
setuo.ll 1 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
vtx-schedule.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
packetizer.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s
udiv.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
2 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
urem.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
2 ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
vertex-fetch-encoding.ll 1 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=barts | FileCheck --check-prefix=NI-CHECK %s
2 ; RUN: not llc < %s -march=r600 -show-mc-encoding -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
schedule-vs-if-nested-loop.ll 1 ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
6 %0 = call float @llvm.R600.load.input(i32 4)
7 %1 = call float @llvm.R600.load.input(i32 5)
8 %2 = call float @llvm.R600.load.input(i32 6)
9 %3 = call float @llvm.R600.load.input(i32 7)
88 call void @llvm.R600.store.swizzle(<4 x float> %74, i32 60, i32 1)
93 call void @llvm.R600.store.swizzle(<4 x float> %78, i32 0, i32 2)
130 declare float @llvm.R600.load.input(i32) #0
132 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
jump-address.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
39 call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0)
50 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
llvm.AMDGPU.cube.ll 2 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
42 call void @llvm.R600.store.swizzle(<4 x float> %30, i32 0, i32 0)
55 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
mul_uint24.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
3 ; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
schedule-fs-loop.ll 1 ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched
41 call void @llvm.R600.store.swizzle(<4 x float> %24, i32 0, i32 0)
53 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
  /external/mesa3d/src/gallium/drivers/radeon/
R600MachineFunctionInfo.cpp 1 //===-- R600MachineFunctionInfo.cpp - R600 Machine Function Info-*- C++ -*-===//
R600Schedule.td 1 //===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
10 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
  /external/mesa3d/src/gallium/targets/va-r600/
Makefile 10 $(TOP)/src/gallium/drivers/r600/libr600.a \
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600Schedule.td 1 //===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
10 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
  /external/llvm/lib/Target/R600/
Processors.td 1 //===-- Processors.td - R600 Processor definitions ------------------------===//
14 def : Proc<"r600", R600_VLIW5_Itin,
  /external/chromium_org/third_party/mesa/src/src/gallium/targets/egl-static/
egl_pipe.c 41 /* for r600 */
42 #include "r600/r600_public.h"
191 else if (strcmp(name, "r600") == 0)

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