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    Searched full:sext (Results 426 - 450 of 729) sorted by null

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/external/llvm/test/Transforms/LoopVectorize/
vectorize-once.ll	24 %idx.ext = sext i32 %n to i64 50 %idx.ext = sext i32 %n to i64
/external/llvm/test/Analysis/DependenceAnalysis/
Preliminary.ll	441 %conv2 = sext i8 %i.03 to i32 442 %conv3 = sext i8 %i.03 to i64 446 %idxprom4 = sext i8 %i.03 to i64 452 %conv = sext i8 %inc to i64 487 %conv2 = sext i16 %i.03 to i32 488 %conv3 = sext i16 %i.03 to i64 492 %idxprom4 = sext i16 %i.03 to i64 498 %conv = sext i16 %inc to i64 559 %idxprom = sext i8 %n to i64 570 %conv = sext i8 %n to i6     [all...]
/external/llvm/test/Transforms/InstCombine/
select.ll	354 ; CHECK-NEXT: sext i32 595 ; CHECK-NEXT: %b = sext i1 %cond to i32 601 %a_ext = sext i32 %a to i64 606 ; CHECK-NEXT: %a_ext = sext i32 %a to i64 613 %a_ext = sext i32 %a to i64 618 ; CHECK-NEXT: %a_ext = sext i32 %a to i64 647 %a_ext = sext i32 %a to i64 652 ; CHECK-NEXT: %a_ext = sext i32 %a to i64 659 %a_ext = sext i32 %a to i64 664 ; CHECK-NEXT: %a_ext = sext i32 %a to i6     [all...]
/external/llvm/test/CodeGen/AArch64/
ldst-unsignedimm.ll	19 %val32_signed = sext i8 %val8_sext32 to i32 38 %val64_signed = sext i8 %val8_sext64 to i64 73 %val32_signed = sext i16 %val16_sext32 to i32 92 %val64_signed = sext i16 %val16_sext64 to i64 138 %val64_signed = sext i32 %val32_sext to i64
/external/llvm/test/CodeGen/R600/
load.ll	33 %1 = sext i8 %0 to i32 62 %1 = sext i16 %0 to i32 132 %1 = sext i32 %0 to i64 164 %1 = sext i8 %0 to i32 208 %1 = sext i16 %0 to i32
schedule-fs-loop.ll	26 %13 = sext i1 %12 to i32
sra.ll	49 %0 = sext i32 %in to i64
/external/llvm/test/CodeGen/SystemZ/
memcpy-02.ll	55 %ext = sext i8 %val to i32 68 %ext = sext i8 %val to i64 118 %ext = sext i16 %val to i32 131 %ext = sext i16 %val to i64 168 %ext = sext i32 %val to i64
/external/clang/test/CodeGen/
complex-convert.c	76 // CHECK-NEXT: %[[VAR23:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR22]] to i[[LLSIZE]] 98 // CHECK-NEXT: %[[VAR33:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR32]] to i[[LLSIZE]] 179 // CHECK-NEXT: %[[VAR70:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR69]] to i[[LLSIZE]] 209 // CHECK-NEXT: %[[VAR81:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR80]] to i[[LLSIZE]] 239 // CHECK-NEXT: %[[VAR95:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR94]] to i[[ARSIZE:[0-9]+]] 244 // CHECK-NEXT: %[[VAR100:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR97]] to i[[ARSIZE]] 245 // CHECK-NEXT: %[[VAR101:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR99]] to i[[ARSIZE]] 257 // CHECK-NEXT: %[[VAR109:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR108]] to i[[ARSIZE]] 275 // CHECK-NEXT: %[[VAR123:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR122]] to i[[LLSIZE]] 289 // CHECK-NEXT: %[[VAR133:[A-Za-z0-9.]+]] = sext i[[CHSIZE]] %[[VAR132]] to i[[LLSIZE]     [all...]
/frameworks/rs/driver/runtime/
convert.ll	353 %1 = sext <4 x i8> %in to <4 x i16> 358 %1 = sext <3 x i8> %in to <3 x i16> 363 %1 = sext <2 x i8> %in to <2 x i16> 561 %1 = sext <4 x i8> %in to <4 x i32> 566 %1 = sext <3 x i8> %in to <3 x i32> 571 %1 = sext <2 x i8> %in to <2 x i32> 591 %1 = sext <4 x i16> %in to <4 x i32> 596 %1 = sext <3 x i16> %in to <3 x i32> 601 %1 = sext <2 x i16> %in to <2 x i32>
/external/llvm/test/CodeGen/PowerPC/
Atomics-32.ll	541 %9 = sext i8 %8 to i16 548 %15 = sext i8 %14 to i16 555 %21 = sext i8 %20 to i32 562 %27 = sext i8 %26 to i32 569 %33 = sext i8 %32 to i32 576 %39 = sext i8 %38 to i32 595 %55 = sext i8 %54 to i16 604 %63 = sext i8 %62 to i16 613 %71 = sext i8 %70 to i32 622 %79 = sext i8 %78 to i3     [all...]
Atomics-64.ll	548 %9 = sext i8 %8 to i16 555 %15 = sext i8 %14 to i16 562 %21 = sext i8 %20 to i32 569 %27 = sext i8 %26 to i32 576 %33 = sext i8 %32 to i64 583 %39 = sext i8 %38 to i64 604 %57 = sext i8 %56 to i16 614 %66 = sext i8 %65 to i16 624 %75 = sext i8 %74 to i32 634 %84 = sext i8 %83 to i3     [all...]
asym-regclass-copy.ll	25 %conv = sext i32 %add to i64
ppc64-toc.ll	47 %idxprom = sext i32 %i to i64
structsinregs.ll	80 %conv2 = sext i16 %1 to i32 84 %conv4 = sext i16 %2 to i32 167 %conv2 = sext i16 %1 to i32 171 %conv4 = sext i16 %2 to i32
/external/clang/lib/CodeGen/
README.txt	10 generates an zext/sext of x which can easily be avoided.
/external/llvm/bindings/python/llvm/
enumerations.py	93 ('SExt', 32),
/external/llvm/lib/Target/Hexagon/
HexagonRemoveSZExtArgs.cpp	59 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt)) {
/external/llvm/lib/Target/NVPTX/
NVPTXISelDAGToDAG.h	37 // If true, generate mul.wide from sext and mul
/external/llvm/test/Analysis/CostModel/X86/
loop_v2.ll	16 %3 = sext <2 x i32> %2 to <2 x i64>
/external/llvm/test/CodeGen/ARM/
shifter_operand.ll	69 %2 = sext i16 %addr to i32
/external/llvm/test/CodeGen/Mips/
mips64load-store-left-right.ll	31 %conv = sext i32 %0 to i64
/external/llvm/test/CodeGen/Thumb2/
2010-08-10-VarSizedAllocaBug.ll	20 %4 = sext i8 %3 to i32 ; <i32> [#uses=1]
/external/llvm/test/CodeGen/X86/
2007-10-12-SpillerUnfold2.ll	12 %tmp180181 = sext i16 0 to i32 ; <i32> [#uses=1]
2008-03-13-TwoAddrPassCrash.ll	62 %tmp167168 = sext i16 %wMB.0.reg2mem.2 to i32 ; <i32> [#uses=0]

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