/external/chromium_org/v8/src/arm/ |
regexp-macro-assembler-arm.cc | 673 __ sub(r0, r0, Operand(r1, LSL, (mode_ == UC16) ? 1 : 0)); [all...] |
assembler-arm.cc | 379 shift_op_ = LSL; [all...] |
simulator-arm.cc | [all...] |
full-codegen-arm.cc | [all...] |
/external/v8/src/arm/ |
regexp-macro-assembler-arm.cc | 677 __ sub(r0, r0, Operand(r1, LSL, (mode_ == UC16) ? 1 : 0)); [all...] |
assembler-arm.cc | 218 shift_op_ = LSL; [all...] |
simulator-arm.cc | [all...] |
/art/compiler/utils/arm/ |
assembler_arm.cc | [all...] |
/external/valgrind/main/none/tests/arm/ |
v6intARM.stdout.exp | 37 LSL 38 lsl r0, r1, r2 :: rd 0xffffffff rm 0xffffffff, rn 0x00000000, carryin 0, cpsr 0x00000000 39 lsl r0, r1, r2 :: rd 0xfffffffe rm 0xffffffff, rn 0x00000001, carryin 0, cpsr 0x00000000 40 lsl r0, r1, r2 :: rd 0xfffffffc rm 0xffffffff, rn 0x00000002, carryin 0, cpsr 0x00000000 41 lsl r0, r1, r2 :: rd 0x80000000 rm 0xffffffff, rn 0x0000001f, carryin 0, cpsr 0x00000000 42 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000020, carryin 0, cpsr 0x00000000 43 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000021, carryin 0, cpsr 0x00000000 44 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x0000003f, carryin 0, cpsr 0x00000000 45 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x00000040, carryin 0, cpsr 0x00000000 46 lsl r0, r1, r2 :: rd 0x00000000 rm 0xffffffff, rn 0x000000ff, carryin 0, cpsr 0x00000000 [all...] |
/external/chromium_org/third_party/mesa/src/src/mesa/x86/ |
assyntax.h | 526 #define LSL(a, b) CHOICE(lsl ARG2(a,b), lsl ARG2(a,b), lsl ARG2(b,a)) [all...] |
/external/mesa3d/src/mesa/x86/ |
assyntax.h | 526 #define LSL(a, b) CHOICE(lsl ARG2(a,b), lsl ARG2(a,b), lsl ARG2(b,a)) [all...] |
/external/llvm/test/MC/ARM/ |
basic-thumb2-instructions.s | 48 adcs r0, r1, r3, lsl #7 58 @ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10] 119 adds r7, r3, r1, lsl #31 127 @ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77] 167 ands r2, r1, r7, lsl #1 173 @ CHECK: ands.w r2, r1, r7, lsl #1 @ encoding: [0x11,0xea,0x47,0x02] 263 bic r11, r2, r6, lsl #12 272 bic r4, r2, lsl #31 280 @ CHECK: bic.w r11, r2, r6, lsl #12 @ encoding: [0x22,0xea,0x06,0x3b] 288 @ CHECK: bic.w r4, r4, r2, lsl #31 @ encoding: [0x24,0xea,0xc2,0x74 [all...] |
basic-arm-instructions.s | 50 adc r4, r5, r6, lsl #1 51 adc r4, r5, r6, lsl #31 62 adc r6, r7, r8, lsl r9 70 adc r4, r5, lsl #1 71 adc r4, r5, lsl #31 81 adc r6, r7, lsl r9 89 @ CHECK: adc r4, r5, r6, lsl #1 @ encoding: [0x86,0x40,0xa5,0xe0] 90 @ CHECK: adc r4, r5, r6, lsl #31 @ encoding: [0x86,0x4f,0xa5,0xe0] 100 @ CHECK: adc r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0xa7,0xe0] 107 @ CHECK: adc r4, r4, r5, lsl #1 @ encoding: [0x85,0x40,0xa4,0xe0 [all...] |