| /external/llvm/test/MC/ARM/ |
| neon-bitcount-encoding.s | 11 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3]
12 vclz.i32 d16, d16
17 @ CHECK: vclz.i32 q8, q8 @ encoding: [0xe0,0x04,0xf8,0xf3]
18 vclz.i32 q8, q8
|
| neont2-bitcount-encoding.s | 13 vclz.i32 d16, d16
16 vclz.i32 q8, q8
20 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x04]
23 @ CHECK: vclz.i32 q8, q8 @ encoding: [0xf8,0xff,0xe0,0x04]
|
| neon-mul-accum-encoding.s | 5 vmla.i32 d16, d18, d17
9 vmla.i32 q9, q8, q10
11 vmla.i32 q12, q8, d3[0]
15 @ CHECK: vmla.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf2]
19 @ CHECK: vmla.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf2]
21 @ CHECK: vmla.i32 q12, q8, d3[0] @ encoding: [0xc3,0x80,0xe0,0xf3]
56 vmls.i32 d16, d18, d17
60 vmls.i32 q9, q8, q10
66 @ CHECK: vmls.i32 d16, d18, d17 @ encoding: [0xa1,0x09,0x62,0xf3]
70 @ CHECK: vmls.i32 q9, q8, q10 @ encoding: [0xe4,0x29,0x60,0xf3
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/ |
| h264bsd_intra_prediction.h | 57 u32 h264bsdIntra16x16Prediction(mbStorage_t *pMb, u8 *data, i32 residual[][16],
60 u32 h264bsdIntraChromaPrediction(mbStorage_t *pMb, u8 *data, i32 residual[][16],
|
| h264bsd_sei.h | 81 i32 timeOffset[MAX_NUM_CLOCK_TS];
89 i32 panScanRectLeftOffset[MAX_PAN_SCAN_CNT];
90 i32 panScanRectRightOffset[MAX_PAN_SCAN_CNT];
91 i32 panScanRectTopOffset[MAX_PAN_SCAN_CNT];
92 i32 panScanRectBottomOffset[MAX_PAN_SCAN_CNT];
|
| h264bsd_slice_data.c | 53 i32 chromaQpIndexOffset);
99 i32 qpY;
129 qpY = (i32)pStorage->activePps->picInitQp + pSliceHeader->sliceQpDelta;
254 i32 chromaQpIndexOffset)
259 i32 tmp2, tmp3;
|
| h264bsd_slice_group_map.c | 305 i32 x, y, xDir, yDir, leftBound, topBound, rightBound, bottomBound;
329 xDir = (i32)sliceGroupChangeDirectionFlag - 1;
330 yDir = (i32)sliceGroupChangeDirectionFlag;
345 yDir = 2 * (i32)sliceGroupChangeDirectionFlag - 1;
349 rightBound = MIN(rightBound + 1, (i32)picWidth - 1);
352 yDir = 1 - 2 * (i32)sliceGroupChangeDirectionFlag;
358 xDir = 1 - 2 * (i32)sliceGroupChangeDirectionFlag;
363 bottomBound = MIN(bottomBound + 1, (i32)picHeight - 1);
365 xDir = 2 * (i32)sliceGroupChangeDirectionFlag - 1;
|
| h264bsd_macroblock_layer.c | 108 static u32 ProcessResidual(mbStorage_t *pMb, i32 residualLevel[][16], u32 *);
141 i32 itmp;
172 i32 *level;
187 *level++ = (i32)value;
360 i32 itmp;
448 i32 itmp;
706 i32 nc;
710 i32 (*level)[16];
722 nc = (i32)DetermineNc(pMb, 0, pResidual->totalCoeff);
741 nc = (i32)DetermineNc(pMb, blockIndex, pResidual->totalCoeff)
[all...] |
| h264bsd_deblocking.c | 182 i32 imageWidth);
184 i32 imageWidth);
189 i32 imageWidth);
191 i32 imageWidth);
202 i32 chromaQpIndexOffset);
223 i32 chromaQpIndexOffset);
333 i32 tmp1, tmp2;
334 i32 mv1, mv2, mv3, mv4;
368 i32 tmp1, tmp2, tmp3, tmp4;
658 i32 delta, tc, tmp
[all...] |
| h264bsd_storage.h | 68 i32 prevDeltaPicOrderCntBottom;
69 i32 prevDeltaPicOrderCnt[2];
|
| h264bsd_seq_param_set.c | 206 pSeqParamSet->numRefFramesInPicOrderCntCycle, i32);
291 if ( ( (i32)pSeqParamSet->frameCropLeftOffset >
292 ( 8 * (i32)pSeqParamSet->picWidthInMbs -
293 ((i32)pSeqParamSet->frameCropRightOffset + 1) ) ) ||
294 ( (i32)pSeqParamSet->frameCropTopOffset >
295 ( 8 * (i32)pSeqParamSet->picHeightInMbs -
296 ((i32)pSeqParamSet->frameCropBottomOffset + 1) ) ) )
|
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
344 MVT::i32,
346 DAG.getConstant(-1, MVT::i32),
347 DAG.getConstant(0, MVT::i32),
369 DAG.getConstant(ByteOffset, MVT::i32), // PTR
383 DAG.getConstant(32, MVT::i32),
[all...] |
| AMDILISelDAGToDAG.cpp | 97 return CurDAG->getTargetConstant(Imm, MVT::i32);
105 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
106 R2 = CurDAG->getTargetConstant(0, MVT::i32);
109 R2 = CurDAG->getTargetConstant(0, MVT::i32);
116 R2 = CurDAG->getTargetConstant(0, MVT::i32);
167 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
343 MVT::i32);
351 Offset = CurDAG->getTargetConstant(0, MVT::i32);
365 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
372 AMDGPU::ZERO, MVT::i32);
[all...] |
| R600GenRegisterInfo.pl | 77 def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
80 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
83 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add
86 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
91 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
94 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 33 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
36 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
43 setOperationAction(ISD::ROTL, MVT::i32, Custom);
46 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
344 MVT::i32,
346 DAG.getConstant(-1, MVT::i32),
347 DAG.getConstant(0, MVT::i32),
369 DAG.getConstant(ByteOffset, MVT::i32), // PTR
383 DAG.getConstant(32, MVT::i32),
[all...] |
| AMDILISelDAGToDAG.cpp | 97 return CurDAG->getTargetConstant(Imm, MVT::i32);
105 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
106 R2 = CurDAG->getTargetConstant(0, MVT::i32);
109 R2 = CurDAG->getTargetConstant(0, MVT::i32);
116 R2 = CurDAG->getTargetConstant(0, MVT::i32);
167 SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32);
343 MVT::i32);
351 Offset = CurDAG->getTargetConstant(0, MVT::i32);
365 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
372 AMDGPU::ZERO, MVT::i32);
[all...] |
| R600GenRegisterInfo.pl | 77 def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
80 def R600_TReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
83 def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add
86 def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add
91 def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add
94 def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 34 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
92 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
94 setOperationAction(ISD::MULHS, MVT::i32, Custom);
95 setOperationAction(ISD::MULHU, MVT::i32, Custom);
106 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
107 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
111 setOperationAction(ISD::LOAD, MVT::i32, Custom);
112 setOperationAction(ISD::STORE, MVT::i32, Custom);
133 case MVT::i32
[all...] |
| MipsISelLowering.cpp | 220 // Mips does not have i1 type, so use i32 for
238 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
243 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
245 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
249 setOperationAction(ISD::SELECT, MVT::i32, Custom);
258 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
278 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 262 case MVT::i32:
291 case MVT::i32:
321 case MVT::i32:
344 case MVT::i32:
373 case MVT::i32:
396 case MVT::i32:
504 case MVT::i32:
528 case MVT::i32:
558 case MVT::i32:
582 case MVT::i32
[all...] |
| NVPTXISelLowering.cpp | 127 addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
139 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
144 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
157 setOperationAction(ISD::ROTL, MVT::i32, Legal);
158 setOperationAction(ISD::ROTR, MVT::i32, Legal);
160 setOperationAction(ISD::ROTL, MVT::i32, Expand);
161 setOperationAction(ISD::ROTR, MVT::i32, Expand);
169 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
177 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
196 setTruncStoreAction(MVT::i32, MVT::i1, Expand)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 107 LocVT = MVT::i32;
108 ValVT = MVT::i32;
116 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
145 LocVT = MVT::i32;
146 ValVT = MVT::i32;
155 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
220 LocVT = MVT::i32;
221 ValVT = MVT::i32;
230 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
247 if (LocVT == MVT::i32 || LocVT == MVT::f32)
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 35 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass);
56 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
66 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
68 setOperationAction(ISD::SETCC, MVT::i32, Expand);
72 setOperationAction(ISD::SELECT, MVT::i32, Custom);
76 setOperationAction(ISD::LOAD, MVT::i32, Custom);
84 setOperationAction(ISD::STORE, MVT::i32, Custom);
88 setOperationAction(ISD::LOAD, MVT::i32, Custom);
90 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
98 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom)
[all...] |
| /external/clang/test/Lexer/ |
| ms-extensions.c | 6 __int32 x3 = 5i32;
|
| /frameworks/av/libvideoeditor/osal/src/ |
| M4OSA_CharStar.c | 92 M4OSA_UInt32 i32,len32; local
109 for(i32=0;i32<len32;i32++)
111 if(pStrIn1[i32] != pStrIn2[i32])
|
