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  /external/llvm/lib/Target/XCore/
README.txt 4 * Instruction encodings
  /art/compiler/dex/
local_value_numbering.cc 26 case Instruction::NOP:
27 case Instruction::RETURN_VOID:
28 case Instruction::RETURN:
29 case Instruction::RETURN_OBJECT:
30 case Instruction::RETURN_WIDE:
31 case Instruction::MONITOR_ENTER:
32 case Instruction::MONITOR_EXIT:
33 case Instruction::GOTO:
34 case Instruction::GOTO_16:
35 case Instruction::GOTO_32
    [all...]
dex_to_dex_compiler.cc 66 void CompileReturnVoid(Instruction* inst, uint32_t dex_pc);
69 // this case, returns the second NOP instruction pointer. Otherwise, returns
71 Instruction* CompileCheckCast(Instruction* inst, uint32_t dex_pc);
79 void CompileInstanceFieldAccess(Instruction* inst, uint32_t dex_pc,
80 Instruction::Code new_opcode, bool is_put);
88 void CompileInvokeVirtual(Instruction* inst, uint32_t dex_pc,
89 Instruction::Code new_opcode, bool is_range);
103 Instruction* inst = const_cast<Instruction*>(Instruction::At(insns))
    [all...]
  /external/llvm/lib/Transforms/InstCombine/
InstCombine.h 43 if (isa<Instruction>(V)) {
64 void InsertHelper(Instruction *I, const Twine &Name,
74 public InstVisitor<InstCombiner, Instruction*> {
106 // Visitation implementation - Implement instruction combining for different
107 // instruction types. The semantics are as follows:
111 // otherwise - Change was made, replace I with returned instruction
113 Instruction *visitAdd(BinaryOperator &I);
114 Instruction *visitFAdd(BinaryOperator &I);
116 Instruction *visitSub(BinaryOperator &I);
117 Instruction *visitFSub(BinaryOperator &I)
    [all...]
  /art/compiler/dex/quick/
mir_to_lir.cc 33 Instruction::Code opcode = mir->dalvikInsn.opcode;
76 case Instruction::NOP:
79 case Instruction::MOVE_EXCEPTION:
83 case Instruction::RETURN_VOID:
94 case Instruction::RETURN:
95 case Instruction::RETURN_OBJECT:
102 case Instruction::RETURN_WIDE:
109 case Instruction::MOVE_RESULT_WIDE:
115 case Instruction::MOVE_RESULT:
116 case Instruction::MOVE_RESULT_OBJECT
    [all...]
  /dalvik/dx/tests/031-bb-dead-code/
info.txt 2 dead code. There is at least one example of dead code after each instruction
3 that *doesn't* flow to the next instruction.
  /external/chromium_org/third_party/yasm/source/patched-yasm/modules/arch/x86/tests/
nomem64-err2.errwarn 1 -:2: error: cannot use A/B/C/DH with instruction needing REX
2 -:3: error: cannot use A/B/C/DH with instruction needing REX
sse4-err.errwarn 1 -:2: error: cannot use A/B/C/DH with instruction needing REX
2 -:3: error: cannot use A/B/C/DH with instruction needing REX
cpubasic-err.errwarn 1 -:2: warning: `pause' is an instruction in CPU P4
3 -:7: warning: `fninit' is an instruction in CPU FPU
5 -:16: warning: `movsd' is an instruction in CPU 386
  /external/valgrind/main/none/tests/s390x/
op00.c 1 /* Test for invalid instruction 00. */