Lines Matching full:instruction
86 void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1,
91 case Instruction::IF_EQ:
94 case Instruction::IF_NE:
97 case Instruction::IF_LT:
100 case Instruction::IF_GE:
103 case Instruction::IF_GT:
106 case Instruction::IF_LE:
140 void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken,
145 case Instruction::IF_EQZ:
148 case Instruction::IF_NEZ:
151 case Instruction::IF_LTZ:
154 case Instruction::IF_GEZ:
157 case Instruction::IF_GTZ:
160 case Instruction::IF_LEZ:
182 void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest,
188 case Instruction::INT_TO_BYTE:
191 case Instruction::INT_TO_SHORT:
194 case Instruction::INT_TO_CHAR:
245 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the
294 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set;
1195 void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,
1200 case Instruction::SHL_LONG:
1201 case Instruction::SHL_LONG_2ADDR:
1204 case Instruction::SHR_LONG:
1205 case Instruction::SHR_LONG_2ADDR:
1208 case Instruction::USHR_LONG:
1209 case Instruction::USHR_LONG_2ADDR:
1222 void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
1231 case Instruction::NEG_INT:
1235 case Instruction::NOT_INT:
1239 case Instruction::ADD_INT:
1240 case Instruction::ADD_INT_2ADDR:
1243 case Instruction::SUB_INT:
1244 case Instruction::SUB_INT_2ADDR:
1247 case Instruction::MUL_INT:
1248 case Instruction::MUL_INT_2ADDR:
1251 case Instruction::DIV_INT:
1252 case Instruction::DIV_INT_2ADDR:
1258 case Instruction::REM_INT:
1259 case Instruction::REM_INT_2ADDR:
1264 case Instruction::AND_INT:
1265 case Instruction::AND_INT_2ADDR:
1268 case Instruction::OR_INT:
1269 case Instruction::OR_INT_2ADDR:
1272 case Instruction::XOR_INT:
1273 case Instruction::XOR_INT_2ADDR:
1276 case Instruction::SHL_INT:
1277 case Instruction::SHL_INT_2ADDR:
1281 case Instruction::SHR_INT:
1282 case Instruction::SHR_INT_2ADDR:
1286 case Instruction::USHR_INT:
1287 case Instruction::USHR_INT_2ADDR:
1383 bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div,
1388 // No divide instruction for Arm, so check for more special cases
1473 void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src,
1481 case Instruction::RSUB_INT_LIT8:
1482 case Instruction::RSUB_INT: {
1495 case Instruction::SUB_INT:
1496 case Instruction::SUB_INT_2ADDR:
1499 case Instruction::ADD_INT:
1500 case Instruction::ADD_INT_2ADDR:
1501 case Instruction::ADD_INT_LIT8:
1502 case Instruction::ADD_INT_LIT16:
1505 case Instruction::MUL_INT:
1506 case Instruction::MUL_INT_2ADDR:
1507 case Instruction::MUL_INT_LIT8:
1508 case Instruction::MUL_INT_LIT16: {
1515 case Instruction::AND_INT:
1516 case Instruction::AND_INT_2ADDR:
1517 case Instruction::AND_INT_LIT8:
1518 case Instruction::AND_INT_LIT16:
1521 case Instruction::OR_INT:
1522 case Instruction::OR_INT_2ADDR:
1523 case Instruction::OR_INT_LIT8:
1524 case Instruction::OR_INT_LIT16:
1527 case Instruction::XOR_INT:
1528 case Instruction::XOR_INT_2ADDR:
1529 case Instruction::XOR_INT_LIT8:
1530 case Instruction::XOR_INT_LIT16:
1533 case Instruction::SHL_INT_LIT8:
1534 case Instruction::SHL_INT:
1535 case Instruction::SHL_INT_2ADDR:
1540 case Instruction::SHR_INT_LIT8:
1541 case Instruction::SHR_INT:
1542 case Instruction::SHR_INT_2ADDR:
1547 case Instruction::USHR_INT_LIT8:
1548 case Instruction::USHR_INT:
1549 case Instruction::USHR_INT_2ADDR:
1555 case Instruction::DIV_INT:
1556 case Instruction::DIV_INT_2ADDR:
1557 case Instruction::DIV_INT_LIT8:
1558 case Instruction::DIV_INT_LIT16:
1559 case Instruction::REM_INT:
1560 case Instruction::REM_INT_2ADDR:
1561 case Instruction::REM_INT_LIT8:
1562 case Instruction::REM_INT_LIT16: {
1567 if ((opcode == Instruction::DIV_INT) ||
1568 (opcode == Instruction::DIV_INT_2ADDR) ||
1569 (opcode == Instruction::DIV_INT_LIT8) ||
1570 (opcode == Instruction::DIV_INT_LIT16)) {
1609 void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest,
1620 case Instruction::NOT_LONG:
1636 case Instruction::ADD_LONG:
1637 case Instruction::ADD_LONG_2ADDR:
1645 case Instruction::SUB_LONG:
1646 case Instruction::SUB_LONG_2ADDR:
1654 case Instruction::MUL_LONG:
1655 case Instruction::MUL_LONG_2ADDR:
1665 case Instruction::DIV_LONG:
1666 case Instruction::DIV_LONG_2ADDR:
1672 case Instruction::REM_LONG:
1673 case Instruction::REM_LONG_2ADDR:
1680 case Instruction::AND_LONG_2ADDR:
1681 case Instruction::AND_LONG:
1688 case Instruction::OR_LONG:
1689 case Instruction::OR_LONG_2ADDR:
1697 case Instruction::XOR_LONG:
1698 case Instruction::XOR_LONG_2ADDR:
1706 case Instruction::NEG_LONG: {
