Lines Matching full:opcode
86 void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1,
90 switch (opcode) {
111 LOG(FATAL) << "Unexpected opcode " << opcode;
140 void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken,
144 switch (opcode) {
165 LOG(FATAL) << "Unexpected opcode " << opcode;
182 void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest,
187 switch (opcode) {
1195 void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,
1199 switch (opcode) {
1222 void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest,
1230 switch (opcode) {
1292 LOG(FATAL) << "Invalid word arith op: " << opcode;
1473 void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src,
1480 switch (opcode) {
1567 if ((opcode == Instruction::DIV_INT) ||
1568 (opcode == Instruction::DIV_INT_2ADDR) ||
1569 (opcode == Instruction::DIV_INT_LIT8) ||
1570 (opcode == Instruction::DIV_INT_LIT16)) {
1575 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) {
1596 LOG(FATAL) << "Unexpected opcode " << opcode;
1609 void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest,
1619 switch (opcode) {
