Lines Matching full:msr
35 #define __down_op(ptr,fail) ({ __asm__ __volatile__( "@ down_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movmi ip, %0\n" " blmi " #fail : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); })
36 #define __down_op_ret(ptr,fail) ({ unsigned int ret; __asm__ __volatile__( "@ down_op_ret\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%1]\n" " subs lr, lr, %2\n" " str lr, [%1]\n" " msr cpsr_c, ip\n" " movmi ip, %1\n" " movpl ip, #0\n" " blmi " #fail "\n" " mov %0, ip" : "=&r" (ret) : "r" (ptr), "I" (1) : "ip", "lr", "cc"); smp_mb(); ret; })
37 #define __up_op(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movle ip, %0\n" " blle " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
41 #define __down_op_write(ptr,fail) ({ __asm__ __volatile__( "@ down_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " subs lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movne ip, %0\n" " blne " #fail : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
42 #define __up_op_write(ptr,wake) ({ __asm__ __volatile__( "@ up_op_write\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " movcs ip, %0\n" " blcs " #wake : : "r" (ptr), "I" (RW_LOCK_BIAS) : "ip", "lr", "cc"); smp_mb(); })
45 #define __up_op_read(ptr,wake) ({ smp_mb(); __asm__ __volatile__( "@ up_op_read\n" " mrs ip, cpsr\n" " orr lr, ip, #128\n" " msr cpsr_c, lr\n" " ldr lr, [%0]\n" " adds lr, lr, %1\n" " str lr, [%0]\n" " msr cpsr_c, ip\n" " moveq ip, %0\n" " bleq " #wake : : "r" (ptr), "I" (1) : "ip", "lr", "cc"); })
