Lines Matching refs:bridgereg_t
44 typedef u32 bridgereg_t;
64 bridgereg_t _pad_000058;
65 bridgereg_t b_wid_aux_err;
66 bridgereg_t _pad_000060;
67 bridgereg_t b_wid_resp_upper;
69 bridgereg_t _pad_000068;
70 bridgereg_t b_wid_resp_lower;
71 bridgereg_t _pad_000070;
72 bridgereg_t b_wid_tst_pin_ctrl;
74 bridgereg_t _pad_000078[2];
75 bridgereg_t _pad_000080;
76 bridgereg_t b_dir_map;
77 bridgereg_t _pad_000088[2];
79 bridgereg_t _pad_000090;
80 bridgereg_t b_ram_perr;
81 bridgereg_t _pad_000098[2];
82 bridgereg_t _pad_0000A0;
84 bridgereg_t b_arb;
85 bridgereg_t _pad_0000A8[2];
86 bridgereg_t _pad_0000B0;
87 bridgereg_t b_nic;
89 bridgereg_t _pad_0000B8[2];
90 bridgereg_t _pad_0000C0;
91 bridgereg_t b_bus_timeout;
94 bridgereg_t _pad_0000C8;
95 bridgereg_t b_pci_cfg;
96 bridgereg_t _pad_0000D0;
97 bridgereg_t b_pci_err_upper;
99 bridgereg_t _pad_0000D8;
100 bridgereg_t b_pci_err_lower;
101 bridgereg_t _pad_0000E0[8];
105 bridgereg_t _pad_000100;
106 bridgereg_t b_int_status;
107 bridgereg_t _pad_000108;
109 bridgereg_t b_int_enable;
110 bridgereg_t _pad_000110;
111 bridgereg_t b_int_rst_stat;
112 bridgereg_t _pad_000118;
114 bridgereg_t b_int_mode;
115 bridgereg_t _pad_000120;
116 bridgereg_t b_int_device;
117 bridgereg_t _pad_000128;
119 bridgereg_t b_int_host_err;
121 bridgereg_t __pad;
122 bridgereg_t addr;
125 bridgereg_t _pad_000170[36];
127 bridgereg_t __pad;
129 bridgereg_t reg;
132 bridgereg_t __pad;
134 bridgereg_t reg;
137 bridgereg_t __pad;
139 bridgereg_t reg;
144 bridgereg_t _pad_000290;
145 bridgereg_t b_resp_status;
146 bridgereg_t _pad_000298;
147 bridgereg_t b_resp_clear;
149 bridgereg_t _pad_0002A0[24];
155 bridgereg_t _p_pad;
156 bridgereg_t rd;
162 bridgereg_t _p_pad;
164 bridgereg_t rd;
