Lines Matching refs:x7
82 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7
95 #define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7
385 #define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7
395 #define TIMPANI_TXFE_CLT_RESERVED_M 0x7
617 #define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7
791 #define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7
830 #define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_180UA 0x7
869 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_2_0V 0x7
881 #define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_3V 0x7
916 #define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_M 0x7
1004 #define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_1_25UA 0x7
1016 #define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_1_25UA 0x7
1124 #define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_0_0UA 0x7
1136 #define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_0_0UA 0x7
1199 #define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_1875UA 0x7
1221 #define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_1875UA 0x7
1250 #define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7
1262 #define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7
1430 #define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_9_0 0x7
1496 #define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_9_0 0x7
1562 #define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_9_0 0x7
1634 #define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_9_0 0x7
1705 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_9_0DB 0x7
1727 #define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_9_0DB 0x7
2006 #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_M 0x7
2016 #define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_391_V 0x7
2240 #define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_7 0x7
2269 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2047 0x7
2291 #define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2047 0x7
2416 #define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_7 0x7
2445 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2047 0x7
2467 #define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2047 0x7
2502 #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_M 0x7
2510 #define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_220MA 0x7
2649 #define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_1480UA 0x7
2651 #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_M 0x7
2661 #define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_1480UA 0x7
2820 #define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_M 0x7
2856 #define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_M 0x7
2899 #define TIMPANI_ATEST_AUXPGA_RESERVED_M 0x7
2955 #define TIMPANI_ATEST_IDAC_ATEST1_CONN_IDAC_NEG_OUT 0x7
2971 #define TIMPANI_ATEST_IDAC_ATEST2_CONN_M 0x7
2972 #define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_POS_OUT 0x7
3046 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT1_POS_OUT 0x7
3069 #define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT1_NEG_OUT 0x7
3455 #define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_M 0x7
3509 #define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_M 0x7
4129 #define TIMPANI_CDC_ANC1_RX_NS_M 0x7
4220 #define TIMPANI_CDC_ANC1_SCALE_PTR_M 0x7
4222 #define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_M 0x7
4302 #define TIMPANI_CDC_ANC2_RX_NS_M 0x7
4394 #define TIMPANI_CDC_ANC2_SCALE_PTR_M 0x7
4396 #define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_M 0x7
4519 #define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR 0x7
4544 #define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_M 0x7
4550 #define TIMPANI_CDC_COMP_ZC_MSB_M 0x7
4552 #define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_M 0x7
4572 #define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_M 0x7
