Lines Matching defs:rd
363 Register rd;
364 rd.code_ = (instr & kRdFieldMask) >> kRdShift;
365 return rd;
575 uint32_t rd = GetRd(instr);
585 rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
852 Register rd,
855 ASSERT(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
857 | (rd.code() << kRdShift) | (sa << kSaShift) | func;
1168 void Assembler::jalr(Register rs, Register rd) {
1171 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
1206 void Assembler::addu(Register rd, Register rs, Register rt) {
1207 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
1211 void Assembler::addiu(Register rd, Register rs, int32_t j) {
1212 GenInstrImmediate(ADDIU, rs, rd, j);
1216 void Assembler::subu(Register rd, Register rs, Register rt) {
1217 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
1221 void Assembler::mul(Register rd, Register rs, Register rt) {
1222 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
1248 void Assembler::and_(Register rd, Register rs, Register rt) {
1249 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
1259 void Assembler::or_(Register rd, Register rs, Register rt) {
1260 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
1270 void Assembler::xor_(Register rd, Register rs, Register rt) {
1271 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
1281 void Assembler::nor(Register rd, Register rs, Register rt) {
1282 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
1287 void Assembler::sll(Register rd,
1295 ASSERT(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
1296 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
1300 void Assembler::sllv(Register rd, Register rt, Register rs) {
1301 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
1305 void Assembler::srl(Register rd, Register rt, uint16_t sa) {
1306 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL);
1310 void Assembler::srlv(Register rd, Register rt, Register rs) {
1311 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
1315 void Assembler::sra(Register rd, Register rt, uint16_t sa) {
1316 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA);
1320 void Assembler::srav(Register rd, Register rt, Register rs) {
1321 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
1325 void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
1327 ASSERT(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1330 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
1335 void Assembler::rotrv(Register rd, Register rt, Register rs) {
1337 ASSERT(rd.is_valid() && rt.is_valid() && rs.is_valid() );
1340 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
1356 void Assembler::lb(Register rd, const MemOperand& rs) {
1358 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
1361 GenInstrImmediate(LB, at, rd, 0); // Equiv to lb(rd, MemOperand(at, 0));
1366 void Assembler::lbu(Register rd, const MemOperand& rs) {
1368 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
1371 GenInstrImmediate(LBU, at, rd, 0); // Equiv to lbu(rd, MemOperand(at, 0));
1376 void Assembler::lh(Register rd, const MemOperand& rs) {
1378 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_);
1381 GenInstrImmediate(LH, at, rd, 0); // Equiv to lh(rd, MemOperand(at, 0));
1386 void Assembler::lhu(Register rd, const MemOperand& rs) {
1388 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_);
1391 GenInstrImmediate(LHU, at, rd, 0); // Equiv to lhu(rd, MemOperand(at, 0));
1396 void Assembler::lw(Register rd, const MemOperand& rs) {
1398 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
1401 GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0));
1406 void Assembler::lwl(Register rd, const MemOperand& rs) {
1407 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
1411 void Assembler::lwr(Register rd, const MemOperand& rs) {
1412 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
1416 void Assembler::sb(Register rd, const MemOperand& rs) {
1418 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_);
1421 GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0));
1426 void Assembler::sh(Register rd, const MemOperand& rs) {
1428 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_);
1431 GenInstrImmediate(SH, at, rd, 0); // Equiv to sh(rd, MemOperand(at, 0));
1436 void Assembler::sw(Register rd, const MemOperand& rs) {
1438 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
1441 GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0));
1446 void Assembler::swl(Register rd, const MemOperand& rs) {
1447 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
1451 void Assembler::swr(Register rd, const MemOperand& rs) {
1452 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
1456 void Assembler::lui(Register rd, int32_t j) {
1458 GenInstrImmediate(LUI, zero_reg, rd, j);
1547 void Assembler::mfhi(Register rd) {
1548 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
1552 void Assembler::mflo(Register rd) {
1553 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
1558 void Assembler::slt(Register rd, Register rs, Register rt) {
1559 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
1563 void Assembler::sltu(Register rd, Register rs, Register rt) {
1564 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
1579 void Assembler::movz(Register rd, Register rs, Register rt) {
1580 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
1584 void Assembler::movn(Register rd, Register rs, Register rt) {
1585 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
1589 void Assembler::movt(Register rd, Register rs, uint16_t cc) {
1592 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1596 void Assembler::movf(Register rd, Register rs, uint16_t cc) {
1599 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1604 void Assembler::clz(Register rd, Register rs) {
1605 // Clz instr requires same GPR number in 'rd' and 'rt' fields.
1606 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
