Lines Matching full:__sse3__
303 // CHECK_PRESCOTT_M32: #define __SSE3__ 1
321 // CHECK_NOCONA_M32: #define __SSE3__ 1
335 // CHECK_NOCONA_M64: #define __SSE3__ 1
351 // CHECK_CORE2_M32: #define __SSE3__ 1
366 // CHECK_CORE2_M64: #define __SSE3__ 1
384 // CHECK_COREI7_M32: #define __SSE3__ 1
402 // CHECK_COREI7_M64: #define __SSE3__ 1
426 // CHECK_COREI7_AVX_M32: #define __SSE3__ 1
448 // CHECK_COREI7_AVX_M64: #define __SSE3__ 1
472 // CHECK_CORE_AVX_I_M32: #define __SSE3__ 1
494 // CHECK_CORE_AVX_I_M64: #define __SSE3__ 1
524 // CHECK_CORE_AVX2_M32: #define __SSE3__ 1
552 // CHECK_CORE_AVX2_M64: #define __SSE3__ 1
571 // CHECK_ATOM_M32: #define __SSE3__ 1
586 // CHECK_ATOM_M64: #define __SSE3__ 1
825 // CHECK_K8_SSE3_M32: #define __SSE3__ 1
841 // CHECK_K8_SSE3_M64: #define __SSE3__ 1
891 // CHECK_OPTERON_SSE3_M32: #define __SSE3__ 1
907 // CHECK_OPTERON_SSE3_M64: #define __SSE3__ 1
957 // CHECK_ATHLON64_SSE3_M32: #define __SSE3__ 1
973 // CHECK_ATHLON64_SSE3_M64: #define __SSE3__ 1
1025 // CHECK_AMDFAM10_M32: #define __SSE3__ 1
1044 // CHECK_AMDFAM10_M64: #define __SSE3__ 1
1065 // CHECK_BTVER1_M32: #define __SSE3__ 1
1085 // CHECK_BTVER1_M64: #define __SSE3__ 1
1109 // CHECK_BTVER2_M32: #define __SSE3__ 1
1131 // CHECK_BTVER2_M64: #define __SSE3__ 1
1157 // CHECK_BDVER1_M32: #define __SSE3__ 1
1184 // CHECK_BDVER1_M64: #define __SSE3__ 1
1216 // CHECK_BDVER2_M32: #define __SSE3__ 1
1246 // CHECK_BDVER2_M64: #define __SSE3__ 1
