Lines Matching full:outw
72 outw(RX_DISABLE, BASE + EP_COMMAND);
73 outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);
76 outw(TX_DISABLE, BASE + EP_COMMAND);
77 outw(STOP_TRANSCEIVER, BASE + EP_COMMAND);
79 outw(RX_RESET, BASE + EP_COMMAND);
80 outw(TX_RESET, BASE + EP_COMMAND);
81 outw(C_INTR_LATCH, BASE + EP_COMMAND);
82 outw(SET_RD_0_MASK, BASE + EP_COMMAND);
83 outw(SET_INTR_MASK, BASE + EP_COMMAND);
84 outw(SET_RX_FILTER, BASE + EP_COMMAND);
95 outw(0, BASE + EP_W0_CONFIG_CTRL);
98 outw(SET_IRQ(0), BASE + EP_W0_RESOURCE_CFG);
101 outw(ENABLE_DRQ_IRQ, BASE + EP_W0_CONFIG_CTRL);
109 outw(RX_RESET, BASE + EP_COMMAND);
110 outw(TX_RESET, BASE + EP_COMMAND);
118 outw(ACK_INTR | 0xff, BASE + EP_COMMAND);
120 outw(SET_RD_0_MASK | S_5_INTS, BASE + EP_COMMAND);
122 outw(SET_INTR_MASK, BASE + EP_COMMAND);
124 outw(SET_RX_FILTER | FIL_INDIVIDUAL | FIL_BRDCST, BASE + EP_COMMAND);
128 outw(START_TRANSCEIVER, BASE + EP_COMMAND);
134 outw(ENABLE_UTP, BASE + EP_W4_MEDIA_TYPE);
140 outw(RX_ENABLE, BASE + EP_COMMAND);
141 outw(TX_ENABLE, BASE + EP_COMMAND);
144 outw(SET_RX_EARLY_THRESH | ETH_ZLEN, BASE + EP_COMMAND);
145 outw(SET_TX_START_THRESH | 16, BASE + EP_COMMAND);
187 outw(TX_RESET, BASE + EP_COMMAND);
188 outw(TX_ENABLE, BASE + EP_COMMAND);
196 outw(len, BASE + EP_W1_TX_PIO_WR_1);
197 outw(0x0, BASE + EP_W1_TX_PIO_WR_1); /* Second dword meaningless */
202 outw(t, BASE + EP_W1_TX_PIO_WR_1);
235 outw(ACK_INTR| (cst & S_5_INTS), BASE + EP_COMMAND);
236 outw(C_INTR_LATCH, BASE + EP_COMMAND);
247 outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);
288 outw(RX_DISCARD_TOP_PACK, BASE + EP_COMMAND);
329 outw(EEPROM_CMD_RD | offset, IS_BASE + EP_W0_EEPROM_COMMAND);
601 outw(ntohs(p[i]), BASE + EP_W2_ADDR_0 + (i * 2));
