Lines Matching full:ioaddr
261 #define eepro_full_reset(ioaddr) outb(RESET_CMD, ioaddr); udelay(40);
264 #define eepro_sel_reset(ioaddr) { \
265 outb(SEL_RESET_CMD, ioaddr); \
271 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
274 #define eepro_en_rx(ioaddr) outb(RCV_ENABLE_CMD, ioaddr)
277 #define eepro_dis_rx(ioaddr) outb(RCV_DISABLE_CMD, ioaddr)
280 #define eepro_sw2bank0(ioaddr) outb(BANK0_SELECT, ioaddr)
281 #define eepro_sw2bank1(ioaddr) outb(BANK1_SELECT, ioaddr)
282 #define eepro_sw2bank2(ioaddr) outb(BANK2_SELECT, ioaddr)
288 static unsigned short ioaddr = 0;
301 eepro_sw2bank2(ioaddr); /* be careful, bank2 now */
302 temp_reg = inb(ioaddr + eeprom_reg);
307 outb(temp_reg & 0xEF, ioaddr + eeprom_reg);
309 outb(nic->node_addr[i], ioaddr + I_ADD_REG0 + i);
310 temp_reg = inb(ioaddr + REG1);
313 | RCV_Discard_BadFrame, ioaddr + REG1);
314 temp_reg = inb(ioaddr + REG2); /* match broadcast */
315 outb(temp_reg | 0x14, ioaddr + REG2);
316 temp_reg = inb(ioaddr + REG3);
317 outb(temp_reg & 0x3F, ioaddr + REG3); /* clear test mode */
319 eepro_sw2bank1(ioaddr); /* be careful, bank1 now */
321 outb(RCV_LOWER_LIMIT, ioaddr + RCV_LOWER_LIMIT_REG);
322 outb(RCV_UPPER_LIMIT, ioaddr + RCV_UPPER_LIMIT_REG);
323 outb(XMT_LOWER_LIMIT, ioaddr + xmt_lower_limit_reg);
324 outb(XMT_UPPER_LIMIT, ioaddr + xmt_upper_limit_reg);
325 eepro_sw2bank0(ioaddr); /* Switch back to bank 0 */
326 eepro_clear_int(ioaddr);
328 outw(rx_start = (RCV_LOWER_LIMIT << 8), ioaddr + RCV_BAR);
329 outw(((RCV_UPPER_LIMIT << 8) | 0xFE), ioaddr + RCV_STOP);
331 outw((XMT_LOWER_LIMIT << 8), ioaddr + xmt_bar);
332 eepro_sel_reset(ioaddr);
335 eepro_en_rx(ioaddr);
351 if ((inb(ioaddr + STATUS_REG) & 0x40) == 0)
353 outb(0x40, ioaddr + STATUS_REG);
355 outw(rcv_car, ioaddr + HOST_ADDRESS_REG);
356 rcv_event = inw(ioaddr + IO_PORT);
359 rcv_status = inw(ioaddr + IO_PORT);
360 rcv_next_frame = inw(ioaddr + IO_PORT);
361 rcv_size = inw(ioaddr + IO_PORT);
364 inb(ioaddr + STATUS_REG));
371 insw(ioaddr + IO_PORT, nic->packet, ((rcv_size + 3) >> 1));
383 outw(rcv_car - 1, ioaddr + RCV_STOP);
414 outw(last, ioaddr + HOST_ADDRESS_REG);
415 outw(XMT_CMD, ioaddr + IO_PORT);
416 outw(0, ioaddr + IO_PORT);
417 outw(end, ioaddr + IO_PORT);
418 outw(length, ioaddr + IO_PORT);
419 outsw(ioaddr + IO_PORT, d, ETH_ALEN / 2);
420 outsw(ioaddr + IO_PORT, nic->node_addr, ETH_ALEN / 2);
422 outsw(ioaddr + IO_PORT, &type, sizeof(type) / 2);
423 outsw(ioaddr + IO_PORT, p, (s + 3) >> 1);
425 status = inw(ioaddr + IO_PORT);
426 outw(last, ioaddr + xmt_bar);
427 outb(XMT_CMD, ioaddr);
435 if (((status = inw(ioaddr + IO_PORT)) & TX_DONE_BIT) == 0) {
452 eepro_sw2bank0(ioaddr); /* Switch to bank 0 */
454 outb(STOP_RCV_CMD, ioaddr);
458 eepro_full_reset(ioaddr);
465 int ee_addr = ioaddr + eeprom_reg;
470 eepro_sw2bank1(ioaddr);
471 outb(0x00, ioaddr + STATUS_REG);
473 eepro_sw2bank2(ioaddr);
498 eepro_sw2bank0(ioaddr);
511 id = inb(ioaddr + ID_REG);
515 if (((id = inb(ioaddr + ID_REG)) & R_ROBIN_BITS) != (counter + 0x40))
548 printf("\n%s ioaddr %#hX, addr %!", name, ioaddr, nic->node_addr);
573 for (p = probe_addrs; (ioaddr = *p) != 0; p++) {
