Lines Matching refs:outb
111 outb(D8390_COMMAND_RD2 |
113 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
114 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
115 outb(src, eth_nic_base + D8390_P0_RSAR0);
116 outb(src>>8, eth_nic_base + D8390_P0_RSAR1);
117 outb(D8390_COMMAND_RD0 |
121 outb(src & 0xff, eth_asic_base + _3COM_DALSB);
122 outb(src >> 8, eth_asic_base + _3COM_DAMSB);
123 outb(t503_output | _3COM_CR_START, eth_asic_base + _3COM_CR);
144 outb(t503_output, eth_asic_base + _3COM_CR);
157 outb(D8390_COMMAND_RD2 |
159 outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR);
160 outb(cnt, eth_nic_base + D8390_P0_RBCR0);
161 outb(cnt>>8, eth_nic_base + D8390_P0_RBCR1);
162 outb(dst, eth_nic_base + D8390_P0_RSAR0);
163 outb(dst>>8, eth_nic_base + D8390_P0_RSAR1);
164 outb(D8390_COMMAND_RD1 |
168 outb(dst & 0xff, eth_asic_base + _3COM_DALSB);
169 outb(dst >> 8, eth_asic_base + _3COM_DAMSB);
171 outb(t503_output | _3COM_CR_DDIR | _3COM_CR_START, eth_asic_base + _3COM_CR);
189 outb(*(src++), eth_asic_base + ASIC_PIO);
193 outb(t503_output, eth_asic_base + _3COM_CR);
225 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
228 outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
231 outb(0x49, eth_nic_base+D8390_P0_DCR);
233 outb(0x48, eth_nic_base+D8390_P0_DCR);
234 outb(0, eth_nic_base+D8390_P0_RBCR0);
235 outb(0, eth_nic_base+D8390_P0_RBCR1);
236 outb(0x20, eth_nic_base+D8390_P0_RCR); /* monitor mode */
237 outb(2, eth_nic_base+D8390_P0_TCR);
238 outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
239 outb(eth_rx_start, eth_nic_base+D8390_P0_PSTART);
241 if (eth_flags & FLAG_790) outb(0, eth_nic_base + 0x09);
243 outb(eth_memsize, eth_nic_base+D8390_P0_PSTOP);
244 outb(eth_memsize - 1, eth_nic_base+D8390_P0_BOUND);
245 outb(0xFF, eth_nic_base+D8390_P0_ISR);
246 outb(0, eth_nic_base+D8390_P0_IMR);
249 outb(D8390_COMMAND_PS1 |
253 outb(D8390_COMMAND_PS1 |
256 outb(nic->node_addr[i], eth_nic_base+D8390_P1_PAR0+i);
258 outb(0xFF, eth_nic_base+D8390_P1_MAR0+i);
259 outb(eth_rx_start, eth_nic_base+D8390_P1_CURR);
262 outb(D8390_COMMAND_PS0 |
266 outb(D8390_COMMAND_PS0 |
268 outb(0xFF, eth_nic_base+D8390_P0_ISR);
269 outb(0, eth_nic_base+D8390_P0_TCR);
270 outb(4, eth_nic_base+D8390_P0_RCR); /* allow broadcast frames */
280 outb(t503_output, eth_asic_base + _3COM_CR);
296 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
299 outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
307 outb(0, eth_nic_base+D8390_P0_RBCR0); /* reset byte counter */
308 outb(0, eth_nic_base+D8390_P0_RBCR1);
316 outb(2, eth_nic_base+D8390_P0_TCR);
319 outb(D8390_COMMAND_PS0 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
322 outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
330 outb(D8390_ISR_OVW, eth_nic_base+D8390_P0_ISR);
333 outb(0, eth_nic_base+D8390_P0_TCR);
362 outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
366 outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
378 outb(0, eth_asic_base + WD_MSR);
382 outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
408 outb(D8390_COMMAND_PS0 |
412 outb(D8390_COMMAND_PS0 |
414 outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
415 outb(s, eth_nic_base+D8390_P0_TBCR0);
416 outb(s>>8, eth_nic_base+D8390_P0_TBCR1);
419 outb(D8390_COMMAND_PS0 |
423 outb(D8390_COMMAND_PS0 |
451 outb(D8390_COMMAND_PS1, eth_nic_base+D8390_P0_COMMAND);
453 outb(D8390_COMMAND_PS0, eth_nic_base+D8390_P0_COMMAND);
458 outb(eth_laar | WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
462 outb(WD_MSR_MENB, eth_asic_base + WD_MSR);
503 outb(0, eth_asic_base + WD_MSR);
507 outb(eth_laar & ~WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
515 outb
591 outb(0x80, eth_asic_base + WD_MSR); /* Reset */
598 outb(WD_MSR_MENB, eth_asic_base+WD_MSR);
599 outb((inb(eth_asic_base+0x04) |
601 outb((((unsigned)eth_bmem >> 13) & 0x0F) |
604 outb((inb(eth_asic_base+0x04) &
607 outb((((unsigned)eth_bmem >> 13) & 0x3F) | 0x40, eth_asic_base+WD_MSR);
612 outb(WD_LAAR_M16EN, eth_asic_base + WD_LAAR);
614 outb((eth_laar =
705 outb(_3COM_CR_RST | _3COM_CR_XSEL, eth_asic_base + _3COM_CR );
706 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR );
710 outb(_3COM_CR_EALO | _3COM_CR_XSEL, eth_asic_base + _3COM_CR);
721 outb(_3COM_CR_XSEL, eth_asic_base + _3COM_CR);
726 outb(_3COM_GACFR_RSEL |
729 outb(0xff, eth_asic_base + _3COM_VPTR2);
730 outb(0xff, eth_asic_base + _3COM_VPTR1);
731 outb(0x00, eth_asic_base + _3COM_VPTR0);
747 outb(eth_tx_start, eth_asic_base + _3COM_PSTR);
748 outb(eth_memsize, eth_asic_base + _3COM_PSPR);
775 outb(c, eth_asic_base + NE_RESET);
777 outb(D8390_COMMAND_STP |
779 outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR);
780 outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR);
781 outb(MEM_8192, eth_nic_base + D8390_P0_PSTART);
782 outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP);
795 outb(D8390_DCR_WTS |
797 outb(MEM_16384, eth_nic_base + D8390_P0_PSTART);
798 outb(MEM_32768, eth_nic_base + D8390_P0_PSTOP);
